View PIC16C71-04JW_2509200.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1997 microchip technology inc. ds30272a-page 1 pic16c71x 8-bit cmos microcontrollers with a/d converter devices included in this data sheet: pic16c710 pic16c71 pic16c711 pic16c715 pic16c71x microcontroller core features: high-performance risc cpu only 35 single word instructions to learn all single cycle instructions except for program branches which are two cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle up to 2k x 14 words of program memory, up to 128 x 8 bytes of data memory (ram) interrupt capability eight level deep hardware stack direct, indirect, and relative addressing modes power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode selectable oscillator options low-power, high-speed cmos eprom technology fully static design wide operating voltage range: 2.5v to 6.0v high sink/source current 25/25 ma commercial, industrial and extended temperature ranges program memory parity error checking circuitry with parity error reset (per) (pic16c715) low-power consumption: - < 2 ma @ 5v, 4 mhz - 15 m a typical @ 3v, 32 khz - < 1 m a typical standby current pic16c71x peripheral features: timer0: 8-bit timer/counter with 8-bit prescaler 8-bit multichannel analog-to-digital converter brown-out detection circuitry for brown-out reset (bor) 13 i/o pins with individual direction control pin diagrams pic16c7x features 710 71 711 715 program memory (eprom) x 14 512 1k 1k 2k data memory (bytes) x 8 36 36 68 128 i/o pins 13 13 13 13 timer modules 1 1 1 1 a/d channels 4 4 4 4 in-circuit serial programming yes yes yes yes brown-out reset yes yes yes interrupt sources 4 4 4 4 ra2/an2 ra3/an3/v ref ra4/t0cki mclr /v pp v ss v ss rb0/int rb1 rb2 rb3 ra1/an1 ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ?1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd ssop ra2/an2 ra3/an3/v ref ra4/t0cki mclr /v pp v ss rb0/int rb1 rb2 rb3 ra1/an1 ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ?1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16c710 pdip, soic, windowed cerdip pic16c71 pic16c711 pic16c715 pic16c710 pic16c711 pic16c715
pic16c71x ds30272a -page 2 1997 microchip technology inc. t ab le of contents 1.0 general description ............................................................................................................................... ..................................... 3 2.0 pic16c71x device varieties ............................................................................................................................... ....................... 5 3.0 architectural overview ............................................................................................................................... ................................. 7 4.0 memory organization ............................................................................................................................... ................................ 11 5.0 i/o ports ............................................................................................................................... ..................................................... 25 6.0 timer0 module ............................................................................................................................... ........................................... 31 7.0 analog-to-digital converter (a/d) module ............................................................................................................................... . 37 8.0 special features of the cpu ............................................................................................................................... ..................... 47 9.0 instruction set summary ............................................................................................................................... ........................... 69 10.0 development support ............................................................................................................................... ................................ 85 11.0 electrical characteristics for pic16c710 and pic16c711 ....................................................................................................... 89 12.0 dc and ac characteristics graphs and tables for pic16c710 and pic16c711 .................................................................. 101 13.0 electrical characteristics for pic16c715 ............................................................................................................................... . 111 14.0 dc and ac characteristics graphs and tables for pic16c715 ............................................................................................ 125 15.0 electrical characteristics for pic16c71 ............................................................................................................................... ... 135 16.0 dc and ac characteristics graphs and tables for pic16c71 .............................................................................................. 147 17.0 packaging information ............................................................................................................................... ............................. 155 appendix a: ............................................................................................................................... ....................................................... 161 appendix b: compatibility ............................................................................................................................... .................................. 161 appendix c: what? new ............................................................................................................................... ................................... 162 appendix d: what? changed ............................................................................................................................... ........................... 162 index ............................................................................................................................... ................................................................... 163 pic16c71x product identification system ............................................................................................................................... .......... 173 t o our v alued customers w e constantly str iv e to impro v e the quality of all our products and documentation. w e ha v e spent an e xceptional amount of time to ensure that these documents are correct. ho w e v er , w e realiz e that w e ma y ha v e missed a f e w things . if y ou nd an y inf or mation that is missing or appears in error , please use the reader response f or m in the bac k of this data sheet to inf or m us . w e appreciate y our assistance in making this a better document.
1997 microchip technology inc. ds30272a -page 3 pic16c71x 1.0 general d es cription the pic16c71x is a f amily of lo w-cost, high-perf or- mance , cmos , fully-static , 8-bit microcontrollers with integ r ated analog-to-digital (a/d) con v er ters , in the pic16cxx mid-r ange f amily . all pic16/17 microcontrollers emplo y an adv anced risc architecture . the pic16cxx microcontroller f am- ily has enhanced core f eatures , eight-le v el deep stac k, and m ultiple inter nal and e xter nal interr upt sources . the separ ate instr uction and data b uses of the har v ard architecture allo w a 14-bit wide instr uction w ord with the separ ate 8-bit wide data. the tw o stage instr uction pipeline allo ws all instr uctions to e x ecute in a single cycle , e xcept f or prog r am br anches which require tw o cycles . a total of 35 instr uctions (reduced instr uction set) are a v ailab le . additionally , a large register set giv es some of the architectur al inno v ations used to achie v e a v er y high perf or mance . pic16cxx microcontrollers typically achie v e a 2:1 code compression and a 4:1 speed impro v ement o v er other 8-bit microcontrollers in their class . the pic16c710/71 de vices ha v e 36 b ytes of ram, the pic16c711 has 68 b ytes of ram and the pic16c715 has 128 b ytes of ram. each de vice has 13 i/o pins . in addition a timer/counter is a v ailab le . also a 4-channel high-speed 8-bit a/d is pro vided. the 8-bit resolution is ideally suited f or applications requir ing lo w-cost analog interf ace , e .g. ther mostat control, pressure sensing, etc. the pic16c71x f amily has special f eatures to reduce e xter nal components , thus reducing cost, enhancing system reliability and reducing po w er consumption. there are f our oscillator options , of which the single pin rc oscillator pro vides a lo w-cost solution, the lp oscil- lator minimiz es po w er consumption, xt is a standard cr ystal, and the hs is f or high speed cr ystals . the sleep (po w er-do wn) f eature pro vides a po w er sa ving mode . the user can w ak e up the chip from sleep through se v er al e xter nal and inter nal interr upts and resets . a highly reliab le w atchdog timer with its o wn on-chip rc oscillator pro vides protection against softw are loc k- up . a uv er asab le cerdip pac kaged v ersion is ideal f or code de v elopment while the cost-eff ectiv e one-time- prog r ammab le (o tp) v ersion is suitab le f or production in an y v olume . the pic16c71x f amily ts perf ectly in applications r anging from secur ity and remote sensors to appliance control and automotiv e . the epr om technology mak es customization of application prog r ams (tr ans- mitter codes , motor speeds , receiv er frequencies , etc.) e xtremely f ast and con v enient. the small f ootpr int pac kages mak e this microcontroller ser ies perf ect f or all applications with space limitations . lo w cost, lo w po w er , high perf or mance , ease of use and i/o e xibility mak e the pic16c71x v er y v ersatile e v en in areas where no microcontroller use has been considered bef ore (e .g. timer functions , ser ial comm unication, cap- ture and compare , pwm functions and coprocessor applications). 1.1 f amil y and upwar d co mpatibility users f amiliar with the pic16c5x microcontroller f am- ily will realiz e that this is an enhanced v ersion of the pic16c5x architecture . please ref er to appendix a f or a detailed list of enhancements . code wr itten f or the pic16c5x can be easily por ted to the pic16cxx f am- ily of de vices (appendix b). 1.2 de vel opment suppor t pic16c71x de vices are suppor ted b y the complete line of microchip de v elopment tools . please ref er to section 10.0 f or more details about microchip s de v elopment tools .
pic16c71x ds30272a -page 4 1997 microchip technology inc. t ab le 1-1: pic16c71x f amil y of de vices pic16c710 pic16c71 pic16c711 pic16c715 pic16c72 pic16cr72 (1) clock maximum frequency of operation (mhz) 20 20 20 20 20 20 memory eprom program memory (x14 words) 512 1k 1k 2k 2k rom program memory (14k words) 2k data memory (bytes) 36 36 68 128 128 128 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm module(s) 1 1 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c parallel slave port a/d converter (8-bit) channels 4 4 4 4 5 5 features interrupt sources 4 4 4 4 8 8 i/o pins 13 13 13 13 22 22 voltage range (volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-6.0 3.0-5.5 in-circuit serial programming yes yes yes yes yes yes brown-out reset yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin sdip, soic, ssop 28-pin sdip, soic, ssop pic16c73a pic16c74a pic16c76 pic16c77 clock maximum frequency of operation (mhz) 20 20 20 20 memory eprom program memory (x14 words) 4k 4k 8k 8k data memory (bytes) 192 192 376 376 peripherals timer module(s) tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm module(s) 2 2 2 2 serial port(s) (spi/i 2 c, usart) spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart parallel slave port yes yes a/d converter (8-bit) channels 5 8 5 8 features interrupt sources 11 12 11 12 i/o pins 22 33 22 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 in-circuit serial programming yes yes yes yes brown-out reset yes yes yes yes packages 28-pin sdip, soic 40-pin dip; 44-pin plcc, mqfp, tqfp 28-pin sdip, soic 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 f amily de vices ha v e p o w er-on reset, selectab le w atchdog timer , selectab le code protect and high i/o current capabil- ity . all pic16c7xx f amily de vices use ser ial prog r amming with cloc k pin rb6 and data pin rb7. note 1: please contact y our local microchip sales of ce f or a v ailability of these de vices .
1997 microchip technology inc. ds30272a -page 5 pic16c71x 2.0 pic16c71x de vice v arieties a v ar iety of frequency r anges and pac kaging options are a v ailab le . depending on application and production requirements , the proper de vice option can be selected using the inf or mation in the pic16c71x product iden- ti cation system section at the end of this data sheet. when placing orders , please use that page of the data sheet to specify the correct par t n umber . f or the pic16c71x f amily , there are tw o de vice ?ypes as indicated in the de vice n umber : 1. c , as in pic16 c 71. these de vices ha v e epr om type memor y and oper ate o v er the standard v oltage r ange . 2. lc , as in pic16 lc 71. these de vices ha v e epr om type memor y and oper ate o v er an e xtended v oltage r ange . 2.1 uv erasab le de vices the uv er asab le v ersion, off ered in cerdip pac kage is optimal f or prototype de v elopment and pilot prog r ams . this v ersion can be er ased and reprog r ammed to an y of the oscillator modes . microchip's picst ar t plus and pr o ma te ii prog r ammers both suppor t prog r amming of the pic16c71x . 2.2 one-time-pr ogrammab le (o tp) de vices the a v ailability of o tp de vices is especially useful f or customers who need the e xibility f or frequent code updates and small v olume applications . the o tp de vices , pac kaged in plastic pac kages , per- mit the user to prog r am them once . in addition to the prog r am memor y , the con gur ation bits m ust also be prog r ammed. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip off ers a qtp prog r amming ser vice f or f ac- tor y production orders . this ser vice is made a v ailab le f or users who choose not to prog r am a medium to high quantity of units and whose code patter ns ha v e stabi- liz ed. the de vices are identical to the o tp de vices b ut with all epr om locations and con gur ation options already prog r ammed b y the f actor y . cer tain code and prototype v er i cation procedures apply bef ore produc- tion shipments are a v ailab le . please contact y our local microchip t echnology sales of ce f or more details . 2.4 serializ ed quic k-t urnar ound pr oduction (sqtp sm ) de vices microchip off ers a unique prog r amming ser vice where a f e w user-de ned locations in each de vice are pro- g r ammed with diff erent ser ial n umbers . the ser ial n um- bers ma y be r andom, pseudo-r andom, or sequential. ser ial prog r amming allo ws each de vice to ha v e a unique n umber which can ser v e as an entr y-code , pass w ord, or id n umber .
pic16c71x ds30272a -page 6 1997 microchip technology inc. no tes:
1997 microchip technology inc. ds30272a -page 7 pic16c71x 3.0 ar c hitectural over vie w the high perf or mance of the pic16cxx f amily can be attr ib uted to a n umber of architectur al f eatures com- monly f ound in risc microprocessors . t o begin with, the pic16cxx uses a har v ard architecture , in which, prog r am and data are accessed from separ ate memo- r ies using separ ate b uses . this impro v es bandwidth o v er tr aditional v on neumann architecture in which pro- g r am and data are f etched from the same memor y using the same b us . separ ating prog r am and data b uses fur ther allo ws instr uctions to be siz ed diff erently than the 8-bit wide data w ord. instr uction opcodes are 14-bit s wide making it possib le to ha v e all single w ord instr uctions . a 14-bit wide prog r am memor y access b us f etches a 14-bit instr uction in a single cycle . a tw o- stage pipeline o v er laps f etch and e x ecution of instr uc- tions ( example 3-1 ). consequently , all instr uctions ( 35 ) e x ecute in a single cycle ( 200 ns @ 20 mhz ) e xcept f or prog r am br anches . the tab le belo w lists prog r am memor y (epr om) and data memor y (ram) f or each pic16c71x de vice . the pic16cxx can directly or indirectly address its register les or data memor y . all special function regis- ters , including the prog r am counter , are mapped in the data memor y . the pic16cxx has an or thogonal (sym- metr ical) instr uction set that mak es it possib le to carr y out an y oper ation on an y register using an y addressing mode . this symmetr ical nature and lac k of ?pecial optimal situations mak e prog r amming with the pic16cxx simple y et ef cient. in addition, the lear ning cur v e is reduced signi cantly . de vice pr ogram memor y data memor y pic16c710 512 x 14 36 x 8 pic16c71 1k x 14 36 x 8 pic16c711 1k x 14 68 x 8 pic16c715 2k x 14 128 x 8 pic16cxx de vices contain an 8-bit alu and w or king register . the alu is a gener al pur pose ar ithmetic unit. it perf or ms ar ithmetic and boolean functions betw een the data in the w or king register and an y register le . the alu is 8-bits wide and capab le of addition, sub- tr action, shift and logical oper ations . unless otherwise mentioned, ar ithmetic oper ations are tw o's comple- ment in nature . in tw o-oper and instr uctions , typically one oper and is the w or king register (w register). the other oper and is a le register or an immediate con- stant. in single oper and instr uctions , the oper and is either the w register or a le register . the w register is an 8-bit w or king register used f or alu oper ations . it is not an addressab le register . depending on the instr uction e x ecuted, the alu ma y aff ect the v alues of the carr y (c), digit carr y (dc), and zero (z) bits in the st a tus register . the c and dc bits oper ate as a borro w bit and a digit borro w out bit, respectiv ely , in subtr action. see the sublw and subwf instr uctions f or e xamples .
pic16c71x ds30272a -page 8 1997 microchip technology inc. figure 3-1: pic16c71x bloc k dia gram epr om prog r am memor y 13 data bus 8 14 prog r am bus instr uction reg prog r am counter 8 le v el stac k (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg st a tus reg mux alu w reg p o w er-up timer oscillator star t-up timer p o w er-on reset w atchdog timer instr uction decode & control timing gener ation osc1/clkin osc2/clk out mclr v dd , v ss timer0 a/d por t a por tb rb0/int rb7:rb1 8 8 bro wn-out reset (2) note 1: higher order bits are from the st a tus register . 2: bro wn-out reset is not a v ailab le on the pic16c71. de vice pr ogram memor y data memor y (ram) pic16c710 pic16c71 pic16c711 pic16c715 512 x 14 1k x 14 1k x 14 2k x 14 36 x 8 36 x 8 68 x 8 128 x 8 ra4/t0cki ra3/an3/ v ref ra2/an2 ra1/an1 ra0/an0 8 3
1997 microchip technology inc. ds30272a -page 9 pic16c71x t ab le 3-1: pic16c710/71/711/715 pinout description pin name dip pin# ssop pin# (4) soic pin# i/o/p t ype buff er t ype description osc1/clkin 16 18 16 i st/cmos (3) oscillator cr ystal input/e xter nal cloc k source input. osc2/clk out 15 17 15 o oscillator cr ystal output. connects to cr ystal or resonator in cr ystal oscillator mode . in rc mode , osc2 pin outputs clk out which has 1/4 the frequency of osc1, and denotes the instr uction cycle r ate . mclr / v pp 4 4 4 i/p st master clear (reset) input or p rog r amming v oltage input. this pin is an activ e lo w reset to the de vice . por t a is a bi-directional i/o por t. ra0/an0 17 19 17 i/o ttl ra0 can also be an alog input0 ra1/an1 18 20 18 i/o ttl ra1 can also be an alog input1 ra2/an2 1 1 1 i/o ttl ra2 can also be an alog input2 ra3/an3/ v ref 2 2 2 i/o ttl ra3 can also be an alog input3 or analog ref erence v oltage ra4/t0cki 3 3 3 i/o st ra4 ca n also be t he cloc k input to the timer0 module . output is open dr ain type . por tb is a bi-directional i/o por t. por tb can be softw are pro- g r ammed f or inter nal w eak pull-up on all inputs . rb0/int 6 7 6 i/o ttl/st (1) rb0 c an also be the e xter nal interr upt pin. rb1 7 8 7 i/o ttl rb2 8 9 8 i/o ttl rb3 9 10 9 i/o ttl rb4 10 11 10 i/o ttl interr upt on change pin. rb5 11 12 11 i/o ttl interr upt on change pin. rb6 12 13 12 i/o ttl/st (2) interr upt on change pin. ser ial prog r amming cloc k. rb7 13 14 13 i/o ttl/st (2) interr upt on change pin. ser ial prog r amming data. v ss 5 4, 6 5 p ground ref erence f or logic and i/o pins . v dd 14 15, 16 14 p p ositiv e supply f or logic and i/o pins . legend: i = input o = output i/o = input/output p = po w er ?= not used ttl = ttl input st = schmitt t r igger input note 1: this b uff er is a schmitt t r igger input when con gured as the e xter nal interr upt. 2: this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode . 3: this b uff er is a schmitt t r igger input when con gured in rc oscillator mode and a cmos input otherwise . 4: the pic16c71 is not a v ailab le in ssop pac kage .
pic16c71x ds30272a -page 10 1997 microchip technology inc. 3.1 cloc king sc heme/ instruction cyc le the cloc k input (from osc1) is inter nally divided b y f our to gener ate f our non-o v er lapping quadr ature cloc ks namely q1, q2, q3 and q4. inter nally , the pro- g r am counter (pc) is incremented e v er y q1, the instr uction is f etched from the prog r am memor y and latched into the instr uction register in q4. the instr uc- tion is decoded and e x ecuted dur ing the f ollo wing q1 through q4. the cloc ks and instr uction e x ecution o w is sho wn in figure 3-2 . 3.2 instruction flo w/pipelining an ?nstr uction cycle consists of f our q cycles (q1, q2, q3 and q4). the instr uction f etch and e x ecute are pipelined such that f etch tak es one instr uction cycle while decode and e x ecute tak es another instr uction cycle . ho w e v er , due to the pipelining, each instr uction eff ectiv ely e x ecutes in one cycle . if an instr uction causes the prog r am counter to change (e .g. goto ) then tw o cycles are required to complete the instr uction ( example 3-1 ). a f etch cycle begins with the prog r am counter (pc) incrementing in q1. in the e x ecution cycle , the f etched instr uction is latched into the ?nstr uction register (ir) in cycle q1. this instr uction is then decoded and e x ecuted dur ing the q2, q3, and q4 cycles . data memor y is read dur ing q2 (oper and read) and wr itten dur ing q4 (destination wr ite). figure 3-2: cloc k/instruction cyc le example 3-1: instruction pipeline flo w q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clk out (rc mode) pc pc+1 pc+2 f etch inst (pc) ex ecute inst (pc-1) f etch inst (pc+1) ex ecute inst (pc) f etch inst (pc+2) ex ecute inst (pc+1) inter nal phase cloc k all instr uctions are single cycle , e xcept f or an y prog r am br anches . these tak e tw o cycles since the f etch instr uction is ushed from the pipeline while the ne w instr uction is being f etched and then e x ecuted. tcy0 tcy1 tcy2 tcy3 tcy4 tcy5 1. movlw 55h f etch 1 ex ecute 1 2. movwf portb f etch 2 ex ecute 2 3. call sub_1 f etch 3 ex ecute 3 4. bsf porta, bit3 (forced nop) f etch 4 flush 5. instruction @ address sub_1 f etch sub_1 ex ecute sub_1
1997 microchip technology inc. ds30272a -page 11 pic16c71x 4.0 memor y or ganization 4.1 pr ogram memor y or ganization the pic16c71x f amily has a 13-bit prog r am counter capab le of addressing an 8k x 14 prog r am memor y space . the amount of prog r am memor y a v ailab le to each de vice is listed belo w: f or those de vices with less than 8k prog r am memor y , accessing a location abo v e the ph ysically implemented address will cause a wr aparound. the reset v ector is at 0000h and the interr upt v ector is at 0004h. figure 4-1: pic16c710 pr ogram memor y map and stac k de vice pr ogram memor y ad dress rang e pic16c710 512 x 14 0000h-01ffh pic16c71 1k x 14 0000h-03ffh pic16c711 1k x 14 0000h-03ffh pic16c715 2k x 14 0000h-07ffh pc<12:0> 13 0000h 0004h 0005h 01ffh 0200h 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw user memor y space figure 4-2: pic16c 71/711 pr ogram memor y map and stac k figure 4-3: pic16c715 pr ogram memor y map and stac k pc<12:0> 13 0000h 0004h 0005h 03ffh 0400h 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw user memor y space pc<12:0> 13 0000h 0004h 0005h 07ffh 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw 0800h
pic16c71x ds30272a -page 12 1997 microchip technology inc. 4.2 data memor y or ganization the data memor y is par titioned into tw o banks which contain the gener al pur pose registers and the special function registers . bit rp0 is the bank select bit. rp0 (st a tus<5>) = 1 ? bank 1 rp0 (st a tus<5>) = 0 ? bank 0 each bank e xtends up to 7fh (128 b ytes). the lo w er locations of each bank are reser v ed f or the special function registers . abo v e the special function regis- ters are gener al pur pose registers implemented as static ram. both bank 0 and bank 1 contain special function registers . some "high use" special function registers from bank 0 are mirrored in bank 1 f or code reduction and quic k er access . 4.2.1 gener al pur pose register file the register le can be accessed either directly , or indi- rectly through the file select register fsr ( section 4.5 ). figure 4-4: pic16c710/71 r egister file map indf (1) tmr0 pcl st a tus fsr por t a por tb pcla th intcon adres adcon0 indf (1) option pcl st a tus fsr trisa trisb pcla th intcon adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch gener al pur pose register 7fh ffh bank 0 bank 1 file address adres 2fh 30h afh b0h file address gener al pur pose register mapped in bank 0 (3) pcon (2) unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . 2: the pcon register is not implemented on the pic16c71. 3: these locations are unimplemented in bank 1. an y access to these locations will access the corresponding bank 0 register .
1997 microchip technology inc. ds30272a -page 13 pic16c71x figure 4-5: pic16c711 register file map indf (1) tmr0 pcl st a tus fsr por t a por tb pcla th intcon adres adcon0 indf (1) option pcl st a tus fsr trisa trisb pcla th intcon adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch gener al pur pose register 7fh ffh bank 0 bank 1 file address adres 4fh 50h cfh d0h file address gener al pur pose register mapped in bank 0 (2) pcon unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . 2: these locations are unimplemented in bank 1. an y access to these locations will access the corresponding bank 0 register . figure 4-6: pic16c715 re gister file map indf (1) tmr0 pcl st a tus fsr por t a por tb pcla th intcon pir1 adres adcon0 indf (1) option pcl st a tus fsr trisa trisb pcla th intcon pie1 pcon adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h gener al pur pose register gener al pur pose register 7fh ffh bank 0 bank 1 file address bfh c0h file address unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register .
pic16c71x ds30272a -page 14 1997 microchip technology inc. 4.2.2 special function registers the special function registers are registers used b y the cpu and p er ipher al modules f or controlling the desired oper ation of the de vice . these registers are implemented as static ram. the special function registers can be classi ed into tw o sets (core and per ipher al). those registers associated with the ?ore functions are descr ibed in this section, and those related to the oper ation of the per ipher al f ea- tures are descr ibed in the section of that per ipher al f eature . t ab le 4-1: pic16c710/71/711 special fu nction register summar y ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets (1) bank 0 00h (3) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 01h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 02h (3) pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 03h (3) st a tus irp (5) rp1 (5) rp0 t o pd z dc c 0001 1xxx 000q quuu 04h (3) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 05h por t a por t a data latch when wr itten: por t a pins when read ---x 0000 ---u 0000 06h por tb por tb data latch when wr itten: por tb pins when read xxxx xxxx uuuu uuuu 07h unimplemented 08h adcon0 adcs1 adcs0 (6) chs1 chs0 go/ done adif adon 00-0 0000 00-0 0000 09h (3) adres a/d result register xxxx xxxx uuuu uuuu 0ah (2,3) pcla th wr ite buff er f or the upper 5 bits of the prog r am counter ---0 0000 ---0 0000 0bh (3) intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u bank 1 80h (3) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (3) pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 83h (3) st a tus irp (5) rp1 (5) rp0 t o pd z dc c 0001 1xxx 000q quuu 84h (3) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 85h trisa por t a data direction register ---1 1111 ---1 1111 86h trisb por tb data direction control register 1111 1111 1111 1111 87h (4) pcon por bor ---- --qq ---- --uu 88h adcon1 pcfg1 pcfg0 ---- --00 ---- --00 89h (3) adres a/d result register xxxx xxxx uuuu uuuu 8ah (2,3) pcla th wr ite buff er f or the upper 5 bits of the prog r am counter ---0 0000 ---0 0000 8bh (3) intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u legend: x = unkno wn, u = unchanged, q = v alue depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: other (non po w er-up) resets include e xter nal reset through mclr and w atchdog timer reset. 2: the upper b yte of the prog r am counter is not directly accessib le . pcla th is a holding register f or the pc<12:8> whose contents are tr ansf erred to the upper b yte of the prog r am counter . 3: these registers can be addressed from either bank. 4: the pcon register is not ph ysically implemented in the pic16c71, read as ?? 5: the irp and rp1 bits are reser v ed on the pic16c710/71/711, alw a ys maintain these bits clear . 6: bit5 of adcon0 is a gener al pur pose r/w bit f or the pic16c710/711 only . f or the pic16c71, this bit is unimplemented, read as '0'.
1997 microchip technology inc. ds30272a -page 15 pic16c71x t able 4-2: pic16c715 special function register summar y ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor, per v alue on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 01h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 02h (1) pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 03h (1) st a tus irp (4) rp1 (4) rp0 t o pd z dc c 0001 1xxx 000q quuu 04h (1) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 05h por t a por t a data latch when wr itten: por t a pins when read ---x 0000 ---u 0000 06h por tb por tb data latch when wr itten: por tb pins when read xxxx xxxx uuuu uuuu 07h unimplemented 08h unimplemented 09h unimplemented 0ah (1,2) pcla th wr ite buff er f or the upper 5 bits of the prog r am counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif -0-- ---- -0-- ---- 0dh unimplemented 0eh unimplemented 0fh unimplemented 10h unimplemented 11h unimplemented 12h unimplemented 13h unimplemented 14h unimplemented 15h unimplemented 16h unimplemented 17h unimplemented 18h unimplemented 19h unimplemented 1ah unimplemented 1bh unimplemented 1ch unimplemented 1dh unimplemented 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done adon 0000 00-0 0000 00-0 legend: x = unkno wn, u = unchanged, q = v alue depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper b yte of the prog r am counter is not directly accessib le . pcla th is a holding register f or the pc<12:8> whose contents are tr ansf erred to the upper b yte of the prog r am counter . 3: other (non po w er-up) resets include e xter nal reset through mclr and w atchdog timer reset. 4: the irp and rp1 bits are reser v ed on the pic16c715, alw a ys maintain these bits clear .
pic16c71x ds30272a -page 16 1997 microchip technology inc. bank 1 80h (1) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 83h (1) st a tus irp (4) rp1 (4) rp0 t o pd z dc c 0001 1xxx 000q quuu 84h (1) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 85h trisa por t a data direction register --11 1111 --11 1111 86h trisb por tb data direction register 1111 1111 1111 1111 87h unimplemented 88h unimplemented 89h unimplemented 8ah (1,2) pcla th wr ite buff er f or the upper 5 bits of the pc ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 adie -0-- ---- -0-- ---- 8dh unimplemented 8eh pcon mpeen per por bor u--- -1qq u--- -1uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h unimplemented 93h unimplemented 94h unimplemented 95h unimplemented 96h unimplemented 97h unimplemented 98h unimplemented 99h unimplemented 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh adcon1 pcfg1 pcfg0 ---- --00 ---- --00 t able 4-2: pic16c715 special function register summar y (c ont. d) ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor, per v alue on all other resets (3) legend: x = unkno wn, u = unchanged, q = v alue depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper b yte of the prog r am counter is not directly accessib le . pcla th is a holding register f or the pc<12:8> whose contents are tr ansf erred to the upper b yte of the prog r am counter . 3: other (non po w er-up) resets include e xter nal reset through mclr and w atchdog timer reset. 4: the irp and rp1 bits are reser v ed on the pic16c715, alw a ys maintain these bits clear .
1997 microchip technology inc. ds30272a -page 17 pic16c71x 4.2.2.1 st a tus register the st a tus register , sho wn in figure 4-7 , contains the ar ithmetic status of the alu , the reset status and the bank select bits f or data memor y . the st a tus register can be the destination f or an y instr uction, as with an y other register . if the st a tus register is the destination f or an instr uction that aff ects the z, dc or c bits , then the wr ite to these three bits is disab led. these bits are set or cleared according to the de vice logic. fur ther more , the t o and pd bits are not wr itab le . theref ore , the result of an instr uction with the st a tus register as destination ma y be diff erent than intended. f or e xample , clrf status will clear the upper-three bits and set the z bit. this lea v es the st a tus register as 000u u1uu (where u = unchanged). applicable devices 710 71 711 715 it is recommended, theref ore , that only bcf, bsf, swapf and movwf instr uctions are used to alter the st a tus register because these instr uctions do not aff ect the z, c or dc bits from the st a tus register . f or other instr uctions , not aff ecting an y status bits , see the "instr uction set summar y ." note 1: f or those de vices that do not use bits irp and rp1 (st a tus<7:6>), maintain these bits clear to ensure upw ard compatibility with future products . note 2: the c and dc bits oper ate as a borro w and digit borro w bit, respectiv ely , in sub- tr action. see the sublw and subwf instr uctions f or e xamples . figure 4-7: status r egi ster (ad dress 03 h , 83 h ) r/w -0 r/w -0 r/w -0 r-1 r-1 r/w -x r/w -x r/w -x irp rp1 rp0 t o pd z dc c r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: irp: register bank select bit (used f or indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5: rp1:rp0 : register bank select bits (used f or direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 b ytes bit 4: t o : time-out bit 1 = after po w er-up , clrwdt instr uction, or sleep instr uction 0 = a wdt time-out occurred bit 3: pd : p o w er-do wn bit 1 = after po w er-up or b y the clrwdt instr uction 0 = by e x ecution of the sleep instr uction bit 2: z: zero bit 1 = the result of an ar ithmetic or logic oper ation is z ero 0 = the result of an ar ithmetic or logic oper ation is not z ero bit 1: dc : digit carr y/ borro w bit ( addwf , addlw,sublw,subwf instr uctions)(f or borro w the polar ity is re v ersed) 1 = a carr y-out from the 4th lo w order bit of the result occurred 0 = no carr y-out from the 4th lo w order bit of the result bit 0: c : carr y/ borro w bit ( addwf , addlw,sublw,subwf instr uctions) 1 = a carr y-out from the most signi cant bit of the result occurred 0 = no carr y-out from the most signi cant bit of the result occurred note: f or borro w the polar ity is re v ersed. a subtr action is e x ecuted b y adding the tw o s complement of the second oper and. f or rotate ( rrf , rlf ) instr uctions , this bit is loaded with either the high or lo w order bit of the source register .
pic16c71x ds30272a -page 18 1997 microchip technology inc. 4.2.2.2 option register the option register is a readab le and wr itab le regis- ter which contains v ar ious control bits to con gure the tmr0/wdt prescaler , the exter nal int interr upt, tmr0, and the w eak pull-ups on por tb . applicable devices 710 71 711 715 note: t o achie v e a 1:1 prescaler assignment f or the tmr0 register , assign the prescaler to the w atchdog timer b y setting bit psa (option<3>). figure 4-8: optio n register (ad dress 81 h, 181h ) r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: rbpu : por tb pull-up enab le bit 1 = por tb pull-ups are disab led 0 = por tb pull-ups are enab led b y individual por t latch v alues bit 6: intedg : interr upt edge select bit 1 = interr upt on r ising edge of rb0/int pin 0 = interr upt on f alling edge of rb0/int pin bit 5: t0cs : tmr0 cloc k source select bit 1 = t r ansition on ra4/t0cki pin 0 = inter nal instr uction cycle cloc k (clk out) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-lo w tr ansition on ra4/t0cki pin 0 = increment on lo w-to-high tr ansition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit v alue tmr0 rate wdt rate
1997 microchip technology inc. ds30272a -page 19 pic16c71x 4.2.2.3 intcon register the intcon register is a readab le and wr itab le regis- ter which contains v ar ious enab le and ag bits f or the tmr0 register o v er o w , rb p or t change and exter nal rb0/int pin interr upts . applicable devices 710 71 711 715 note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). figure 4-9: intcon regis ter (ad dress 0b h , 8b h ) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -x gie adie t0ie inte rbie t0if intf rbif r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: gie: (1) global interr upt enab le bit 1 = enab les all un-mask ed interr upts 0 = disab les all interr upts bit 6: adie : a/d con v er ter interr upt enab le bit 1 = enab les a/d interr upt 0 = disab les a/d interr upt bit 5: t0ie : tmr0 ov er o w interr upt enab le bit 1 = enab les the tmr0 interr upt 0 = disab les the tmr0 interr upt bit 4: inte : rb0/int exter nal interr upt enab le bit 1 = enab les the rb0/int e xter nal interr upt 0 = disab les the rb0/int e xter nal interr upt bit 3: rbie : rb p or t change interr upt enab le bit 1 = enab les the rb por t change interr upt 0 = disab les the rb por t change interr upt bit 2: t0if : tmr0 ov er o w interr upt flag bit 1 = tmr0 register has o v er o w ed (m ust be cleared in softw are) 0 = tmr0 register did not o v er o w bit 1: intf : rb0/int exter nal interr upt flag bit 1 = the rb0/int e xter nal interr upt occurred (m ust be cleared in softw are) 0 = the rb0/int e xter nal interr upt did not occur bit 0: rbif : rb p or t change interr upt flag bit 1 = at least one of the rb7:rb4 pins changed state (m ust be cleared in softw are) 0 = none of the rb7:rb4 pins ha v e changed state note 1: f or the pic16c71, if an interr upt occurs while the gie bit is being cleared, the gie bit ma y be uninten- tionally re-enab led b y the retfie instr uction in the user s interr upt ser vice routine . ref er to section 8.5 f or a detailed descr iption. interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). user softw are should ensure the appropr iate interr upt ag bits are clear pr ior to enab ling an interr upt.
pic16c71x ds30272a -page 20 1997 microchip technology inc. 4.2.2.4 pie1 register this register contains the individual enab le bits f or the p er ipher al interr upts . applicable devices 710 71 711 715 note: bit peie (intcon<6>) m ust be set to enab le an y per ipher al interr upt. figure 4-10: pie1 registe r (ad dress 8c h ) u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 u-0 adie r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adie : a/d con v er ter interr upt enab le bit 1 = enab les the a/d interr upt 0 = disab les the a/d interr upt bit 5-0: unimplemented : read as '0'
1997 microchip technology inc. ds30272a -page 21 pic16c71x 4.2.2.5 pir1 register this register contains the individual ag bits f or the p er ipher al interr upts . applicable devices 710 71 711 715 note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). user soft- w are should ensure the appropr iate inter- r upt ag bits are clear pr ior to enab ling an interr upt. figure 4-11: pir1 registe r (ad dress 0c h ) u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 u-0 adif r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adif : a/d con v er ter interr upt flag bit 1 = an a/d con v ersion completed 0 = the a/d con v ersion is not complete bit 5-0: unimplemented : read as '0'
pic16c71x ds30272a -page 22 1997 microchip technology inc. 4.2.2.6 pcon register the p o w er control (pcon) register contains a ag bit to allo w diff erentiation betw een a p o w er-on reset (por) to an e xter nal mclr reset or wdt reset. those de vices with bro wn-out detection circuitr y con- tain an additional bit to diff erentiate a bro wn-out reset (bor) condition from a p o w er-on reset condition. f or the pic16c715 the pcon register also contains status bits mpeen and per. mpeen re ects the v alue of the mpeen bit in the con gur ation w ord. per indicates a par ity error reset has occurred. applicable devices 710 71 711 715 note: bor is unkno wn on p o w er-on reset. it m ust then be set b y the user and chec k ed on subsequent resets to see if bor is clear , indicating a bro wn-out has occurred. the bor status bit is a don't care and is not necessar ily predictab le if the bro wn-out circuit is disab led (b y clear ing the boden bit in the con gur ation w ord). figure 4-12: pcon regi ster (ad dress 8e h ), pic16c710/711 figure 4-13: pcon regi ster (ad dress 8e h ), pic16c715 u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -q por bor r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : p o w er-on reset status bit 1 = no p o w er-on reset occurred 0 = a p o w er-on reset occurred (m ust be set in softw are after a p o w er-on reset occurs) bit 0: bor : bro wn-out reset status bit 1 = no bro wn-out reset occurred 0 = a bro wn-out reset occurred (m ust be set in softw are after a bro wn-out reset occurs) r-u u-0 u-0 u-0 u-0 r/w -1 r/w -0 r/w -q mpeen per por bor (1) r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: mpeen: memor y p ar ity error circuitr y status bit re ects the v alue of con gur ation w ord bit, mpeen bit 6-3: unimplemented: read as '0' bit 2: per : memor y p ar ity error reset status bit 1 = no error occurred 0 = prog r am memor y f etch p ar ity error occurred (m ust be set in softw are after a p ar ity error reset) bit 1: por : p o w er-on reset status bit 1 = no p o w er-on reset occurred 0 = a p o w er-on reset occurred (m ust be set in softw are after a p o w er-on reset occurs) bit 0: bor : bro wn-out reset status bit 1 = no bro wn-out reset occurred 0 = a bro wn-out reset occurred (m ust be set in softw are after a bro wn-out reset occurs)
1997 microchip technology inc. ds30272a -page 23 pic16c71x 4.3 pcl and pcla th the prog r am counter (pc) is 13-bits wide . the lo w b yte comes from the pcl register , which is a readab le and wr itab le register . the upper bits (pc<12:8>) are not readab le , b ut are indirectly wr itab le through the pcla th register . on an y reset, the upper bits of the pc will be cleared. figure 4-14 sho ws the tw o situa- tions f or the loading of the pc . the upper e xample in the gure sho ws ho w the pc is loaded on a wr ite to pcl (pcla th<4:0> ? pch). the lo w er e xample in the gure sho ws ho w the pc is loaded dur ing a call or goto instr uction (pcla th<4:3> ? pch). figure 4-14: loading of pc in diff erent situations 4.3.1 computed go t o a computed go t o is accomplished b y adding an off- set to the prog r am counter ( addwf pcl ). when doing a tab le read using a computed go t o method, care should be e x ercised if the tab le location crosses a pcl memor y boundar y (each 256 b yte b loc k). ref er to the application note ?mplementing a t ab le read" (an 556). pc 12 8 7 0 5 pcla th<4:0> pcla th instr uction with alu goto, call opcode <10:0> 8 pc 12 11 10 0 11 pcla th<4:3> pch pcl 8 7 2 pcla th pch pcl pcl as destination 4.3.2 stac k the pic16cxx f amily has an 8 le v el deep x 13-bit wide hardw are stac k. the stac k space is not par t of either prog r am or data space and the stac k pointer is not readab le or wr itab le . the pc is pushed onto the stac k when a call instr uction is e x ecuted or an interr upt causes a br anch. the stac k is pop ed in the e v ent of a return, retlw or a retfie instr uction e x ecution. pcla th is not aff ected b y a push or pop oper ation. the stac k oper ates as a circular b uff er . this means that after the stac k has been pushed eight times , the ninth push o v erwr ites the v alue that w as stored from the rst push. the tenth push o v erwr ites the second push (and so on). 4.4 pr ogram memor y p a ging the pic16c71x de vices ignore both paging bits (pcla th<4:3>, which are used to access prog r am memor y when more than one page is a v ailab le . the use of pcla th<4:3> as gener al pur pose read/wr ite bits f or the pic16c71x is not recommended since this ma y aff ect upw ard compatibility with future products . note 1: there are no status bits to indicate stac k o v er o w or stac k under o w conditions . note 2: there are no instr uctions/mnemonics calle d push or pop . these are actions that occur from the e x ecution of the call, return, retlw, and retfie instr uc- tions , or the v ector ing to an interr upt address .
pic16c71x ds30272a -page 24 1997 microchip technology inc. example 4-1 sho ws the calling of a subroutine in page 1 of the prog r am memor y . this e xample assumes that pcla th is sa v ed and restored b y the interr upt ser- vice routine (if interr upts are used). example 4-1: call of a subr outine in p a g e 1 fr om p a g e 0 org 0x500 bsf pclath,3 ;select page 1 (800h-fffh) bcf pclath,4 ;only on >4k devices call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : : org 0x900 sub1_p1: ;called subroutine : ;page 1 (800h-fffh) : return ;return to call subroutine ;in page 0 (000h-7ffh) 4.5 indirect ad dressing, indf and fsr register s the indf register is not a ph ysical register . addressing the indf register will cause indirect addressing. indirect addressing is possib le b y using the indf reg- ister . an y instr uction using the indf register actually accesses the register pointed to b y the file select reg- ister , fsr. reading the indf register itself indirectly (fsr = '0') will read 00h. wr iting to the indf register indirectly results in a no-oper ation (although status bits ma y be aff ected). an eff ectiv e 9-bit address is obtained b y concatenating the 8-bit fsr register and the irp bit (st a tus<7>), as sho wn in figure 4-15 . ho w e v er , irp is not used in the pic16c71x de vices . a simple prog r am to clear ram locations 20h-2fh using indirect addressing is sho wn in example 4-2 . example 4-2: indi rect ad dressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue figure 4-15: direct/indi rect ad dressing f or register le map detail see figure 4-4 . note 1: the rp1 and irp bits are reser v ed, alw a ys maintain these bits clear . data memor y indirect ad dressing direct ad dressing bank select location select rp1: rp0 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h not used
1997 microchip technology inc. ds30272a -page 25 pic16c71x 5.0 i/o p or ts some pins f or these i/o por ts are m ultiple x ed with an alter nate function f or the per ipher al f eatures on the de vice . in gener al, when a per ipher al is enab led, that pin ma y not be used as a gener al pur pose i/o pin. 5.1 por t a and trisa register s por t a is a 5-bit latch. the ra4/t0cki pin is a schmitt t r igger input and an open dr ain output. all other ra por t pins ha v e ttl input le v els and full cmos output dr iv ers . all pins ha v e data direction bits (tris registers) which can con gure these pins as output or input. setting a trisa register bit puts the corresponding out- put dr iv er in a hi-impedance mode . clear ing a bit in the trisa register puts the contents of the output latch on the selected pin(s). reading the por t a register reads the status of the pins whereas wr iting to it will wr ite to the por t latch. all wr ite oper ations are read-modify-wr ite oper ations . theref ore a wr ite to a por t implies that the por t pins are read, this v alue is modi ed, and then wr itten to the por t data latch. pin ra4 is m ultiple x ed with the timer0 module cloc k input to become the ra4/t0cki pin. other por t a pins are m ultiple x ed with analog inputs and analog v ref input. the oper ation of each pin is selected b y clear ing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins , e v en when the y are being used as analog inputs . the user m ust ensure the bits in the trisa register are maintained set when using them as analog inputs . example 5-1: initi alizing por t a bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 m ovlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<4> as outputs ; trisa<7:5> are always ; read as '0'. applicable devices 710 71 711 715 note: on a p o w er-on reset, these pins are con- gured as analog inputs and read as '0'. figure 5-1: bloc k dia gram of ra3:ra0 pins figure 5-2: bloc k dia gram of ra4/ t0cki pin data b us q d q ck q d q ck q d en p n wr p o r t wr tris data latch tris latch rd tris rd por t v ss v dd i/o pin (1) note 1: i/o pins ha v e protection diodes to v dd and v ss . analog input mode ttl input b uff er t o a/d con v er ter data b us wr por t wr tris rd por t data latch tris latch rd tris schmitt t r igger input b uff er n v ss i/o pin (1) tmr0 cloc k input note 1: i/o pin has protection diodes to v ss only . q d q ck q d q ck en q d en
pic16c71x ds30272a -page 26 1997 microchip technology inc. t ab le 5-1: por t a functions t ab le 5-2: summar y of register s associated with por t a name bit# buff er function ra0/an0 bit0 ttl input/output or analog input ra1/an1 bit1 ttl input/output or analog input ra2/an2 bit2 ttl input/output or analog input ra3/an3/ v ref bit3 ttl input/output or analog input/v ref ra4/t0cki bit4 st input/output or e xter nal cloc k input f or timer0 output is open dr ain type legend: ttl = ttl input, st = schmitt t r igger input ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 05h por t a ra4 ra3 ra2 ra1 ra0 ---x 0000 ---u 0000 85h trisa por t a data direction register ---1 1111 ---1 1111 9fh adcon1 pcfg1 pcfg0 ---- --00 ---- --00 legend: x = unkno wn, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used b y por t a.
1997 microchip technology inc. ds30272a -page 27 pic16c71x 5.2 por tb and trisb register s por tb is an 8-bit wide bi-directional por t. the corre- sponding data direction register is trisb . setting a bit in the trisb register puts the corresponding output dr iv er in a hi-impedance input mode . clear ing a bit in the trisb register puts the contents of the output latch on the selected pin(s). example 5-2: initia lizing por tb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 m ovlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the por tb pins has a w eak inter nal pull-up . a single control bit can tur n on all the pull-ups . this is perf or med b y clear ing bit rbpu (option<7>). the w eak pull-up is automatically tur ned off when the por t pin is con gured as an output. the pull-ups are dis- ab led on a p o w er-on reset. figure 5-3: bloc k dia gram of rb3:rb0 pins data latch rbpu (2) p v dd q d ck q d ck q d en data b us wr p or t wr tris rd tris rd p or t w eak pull-up rd p or t rb0/int i/o pin (1) ttl input buff er note 1: i/o pins ha v e diode protection to v dd and v ss . 2: trisb = ? enab les w eak pull-up if rbpu = ? (option<7>). schmitt t r igger buff er tris latch f our of por tb s pins , rb7:rb4, ha v e an interr upt on change f eature . only pins con gured as inputs can cause this interr upt to occur (i.e . an y rb7:rb4 pin con- gured as an output is e xcluded from the interr upt on change compar ison). the input pins (of rb7:rb4) are compared with the old v alue latched on the last read of por tb . the ?ismatch outputs of rb7:rb4 are or?d together to gener ate the rb p or t change inter- r upt with ag bit rbif (intcon<0>). this interr upt can w ak e the de vice from sleep . the user , in the interr upt ser vice routine , can clear the inter- r upt in the f ollo wing manner : a) an y read or wr ite of por tb . this will end the mismatch condition. b) clear ag bit rbif . a mismatch condition will contin ue to set ag bit rbif . reading por tb will end the mismatch condition, and allo w ag bit rbif to be cleared. this interr upt on mismatch f eature , together with soft- w are con gur ab le pull-ups on these f our pins allo w easy interf ace to a k e ypad and mak e it possib le f or w ak e-up on k e y-depression. ref er to the embedded control handbook, "implementing w ak e-up on k e y strok e" (an 552). the interr upt on change f eature is recommended f or w ak e-up on k e y depression oper ation and oper ations where por tb is only used f or the interr upt on change f eature . p olling of por tb is not recommended while using the interr upt on change f eature . note: f or the pic16c71 if a change on the i/o pin should occur when the read oper ation is being e x ecuted (star t of the q2 cycle), then interr upt ag bit rbif ma y not get set.
pic16c71x ds30272a -page 28 1997 microchip technology inc. figure 5-4: bloc k dia gram of rb7:rb4 pins (pic16c71) data latch f rom other rbpu (2) p v dd i/o q d ck q d ck q d en q d en data b us wr p or t wr tris set rbif tris latch rd tris rd p or t rb 7 : rb 4 p ins w eak pull-up rd p or t latch ttl input buff er pin (1) st buff er rb7:rb6 in ser ial prog r amming mode note 1: i/o pins ha v e diode protection to v dd and v ss . 2: trisb = ? enab les w eak pull-up if rbpu = ? (option<7>). figure 5-5: bloc k dia gram of rb7:rb4 pins (pic16c710/711/715) data latch f rom other rbpu (2) p v dd i/o q d ck q d ck q d en q d en data b us wr p or t wr tris set rbif tris latch rd tris rd p or t rb 7 : rb 4 p ins w eak pull-up rd p or t latch ttl input buff er pin (1) st buff er rb7:rb6 in ser ial prog r amming mode q3 q1 note 1: i/o pins ha v e diode protection to v dd and v ss . 2: trisb = ? enab les w eak pull-up if rbpu = ? (option<7>). t ab le 5-3: por tb functions name bit# buff er function rb0/int bit0 ttl/st (1) input/output pin or e xter nal interr upt input. inter nal softw are prog r ammab le w eak pull-up . rb1 bit1 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb2 bit2 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb3 bit3 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb4 bit4 ttl input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . rb5 bit5 ttl input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . rb6 bit6 ttl/st (2) input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . ser ial prog r amming cloc k. rb7 bit7 ttl/st (2) input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . ser ial prog r amming data. legend: ttl = ttl input, st = schmitt t r igger input note 1: this b uff er is a schmitt t r igger input when con gured as the e xter nal interr upt. 2: this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode .
1997 microchip technology inc. ds30272a -page 29 pic16c71x t ab le 5-4: summar y of register s associated with por tb ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 06h , 106h por tb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h , 186h trisb por tb data direction register 1111 1111 1111 1111 81h , 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unkno wn, u = unchanged. shaded cells are not used b y por tb .
pic16c71x ds30272a -page 30 1997 microchip technology inc. 5.3 i/o pr ogramming considerations 5.3.1 bi-directional i/o p or ts an y instr uction which wr ites , oper ates inter nally as a read f ollo w ed b y a wr ite oper ation. the bcf and bsf instr uctions , f or e xample , read the register into the cpu , e x ecute the bit oper ation and wr ite the result bac k to the register . caution m ust be used when these instr uctions are applied to a por t with both inputs and outputs de ned. f or e xample , a bsf oper ation on bit5 of por tb will cause all eight bits of por tb to be read into the cpu . then the bsf oper ation tak es place on bit5 and por tb is wr itten to the output latches . if another bit of por tb is used as a bi-directional i/o pin (e .g., bit0) and it is de ned as an input at this time , the input signal present on the pin itself w ould be read into the cpu and re wr itten to the data latch of this par ticular pin, o v erwr iting the pre vious content. as long as the pin sta ys in the input mode , no prob lem occurs . ho w e v er , if bit0 is s witched to an output, the content of the data latch ma y no w be unkno wn. reading the por t register , reads the v alues of the por t pins . wr iting to the por t register wr ites the v alue to the por t latch. when using read-modify-wr ite instr uctions (e x. bcf, bsf , etc.) on a por t, the v alue of the por t pins is read, the desired oper ation is done to this v alue , and this v alue is then wr itten to the por t latch. example 5-3 sho ws the eff ect of tw o sequential read- modify-wr ite instr uctions on an i/o por t. example 5-3: read-modify-write instructions on an i/o p or t ;initial port settings: portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- --------- bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bsf status, rp0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp ; ;note that the user may have expected the ;pin values to be 00pp ppp. the 2nd bcf ;caused rb7 to be latched as the pin value ;(high). a pin activ ely outputting a lo w or high should not be dr iv en from e xter nal de vices at the same time in order to change the le v el on this pin (?ired-or? ?ired-and?. the resulting high output currents ma y damage the chip . 5.3.2 successiv e oper ations on i/o p or ts the actual wr ite to an i/o por t happens at the end of an instr uction cycle , whereas f or reading, the data m ust be v alid at the beginning of the instr uction cycle ( figure 5-6 ). theref ore , care m ust be e x ercised if a wr ite f ollo w ed b y a read oper ation is carr ied out on the same i/o por t. the sequence of instr uctions should be such to allo w the pin v oltage to stabiliz e (load depen- dent) bef ore the ne xt instr uction which causes that le to be read into the cpu is e x ecuted. otherwise , the pre vious state of that pin ma y be read into the cpu r ather than the ne w state . when in doubt, it is better to separ ate these instr uctions with a nop or another instr uction not accessing this i/o por t. figure 5-6: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instr uction f etched rb7:rb0 mo vwf por tb wr ite to por tb nop p or t pin sampled here nop mo vf por tb ,w instr uction e x ecuted mo vwf por tb wr ite to por tb nop mo vf por tb ,w pc t pd note: this e xample sho ws a wr ite to por tb f ollo w ed b y a read from por tb . note that: data setup time = (0. 25t cy - t pd ) where t cy = instr uction cycle t pd = propagation dela y theref ore , at higher cloc k frequencies , a wr ite f ollo w ed b y a read ma y be prob lematic.
1997 microchip technology inc. ds30272a -page 31 pic16c71x 6.0 timer0 module the timer0 module timer/counter has the f ollo wing f ea- tures: 8-bit timer/counter readab le and wr itab le 8-bit softw are prog r ammab le prescaler inter nal or e xter nal cloc k select interr upt on o v er o w from ffh to 00h edge select f or e xter nal cloc k figure 6-1 is a simpli ed b loc k diag r am of the timer0 module . timer mode is selected b y clear ing bit t0cs (option<5>). in timer mode , the timer0 module will increment e v er y instr uction cycle (without prescaler). if the tmr0 register is wr itten, the increment is inhibited f or the f ollo wing tw o instr uction cycles ( figure 6-2 and figure 6-3 ). the user can w or k around this b y wr iting an adjusted v alue to the tmr0 register . counter mode is selected b y setting bit t0cs (option<5>). in counter mode , timer0 will increment either on e v er y r ising or f alling edge of pin ra4/t0cki. the incrementing edge is deter mined b y the timer0 source edge select bit t0se (option<4>). clear ing applicable devices 710 71 711 715 bit t0se selects the r ising edge . restr ictions on the e xter nal cloc k input are discussed in detail in section 6.2 . the prescaler is m utually e xclusiv ely shared betw een the timer0 module and the w atchdog timer . the pres- caler assignment is controlled in softw are b y control bit psa (option<3>). clear ing bit psa will assign the prescaler to the timer0 module . the prescaler is not readab le or wr itab le . when the prescaler is assigned to the timer0 module , prescale v alues of 1:2, 1:4, ..., 1:256 are selectab le . section 6.3 details the oper ation of the prescaler . 6.1 timer0 in terrupt the tmr0 interr upt is gener ated when the tmr0 reg- ister o v er o ws from ffh to 00h. this o v er o w sets bit t0if (intcon<2>). the interr upt can be mask ed b y clear ing bit t0ie (intcon<5>). bit t0if m ust be cleared in softw are b y the timer0 module interr upt ser- vice routine bef ore re-enab ling this interr upt. the tmr0 interr upt cannot a w ak en the processor from sleep since the timer is shut off dur ing sleep . see figure 6-4 f or timer0 interr upt timing. figure 6-1: timer0 blo c k dia gram figure 6-2: timer0 timing: in ternal cloc k/no prescale note 1: t0cs , t0se, psa, ps2:ps0 (option<5:0>). 2: the prescaler is shared with w atchdog timer (ref er to figure 6-6 f or detailed b loc k diag r am). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 prog r ammab le prescaler sync with inter nal cloc ks tmr0 psout (2 cycle dela y) psout data b us 8 psa ps2, ps1, ps0 set interr upt ag bit t0if on o v er o w 3 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 t0 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instr uction ex ecuted
pic16c71x ds30272a -page 32 1997 microchip technology inc. figure 6-3: timer0 timing: internal cloc k/prescale 1:2 figure 6-4: timer0 inter rupt timing pc+ 6 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instr uction ex ecute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clk out (3) timer0 t0if bit (intcon<2>) feh gie bit (intcon<7>) instr uction pc instr uction f etched pc pc +1 pc +1 0004h 0005h instr uction e x ecuted inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dumm y cycle dumm y cycle ffh 00h 01h 02h note 1: interr upt ag bit t0if is sampled here (e v er y q1). 2: interr upt latency = 4tcy where tcy = instr uction cycle time . 3: clk out is a v ailab le only in rc oscillator mode . flo w
1997 microchip technology inc. ds30272a -page 33 pic16c71x 6.2 using timer0 with an external cloc k when an e xter nal cloc k input is used f or timer0, it m ust meet cer tain requirements . the requirements ensure the e xter nal cloc k can be synchroniz ed with the inter nal phase cloc k (t osc ). also , there is a dela y in the actual incrementing of timer0 after synchronization. 6.2.1 exter nal cloc k synchronization when no prescaler is used, the e xter nal cloc k input is the same as the prescaler output. the synchronization of t0cki with the inter nal ph ase cloc ks is accom- plished b y sampling the prescaler output on the q2 and q4 cycles of the inter nal phase cloc ks ( figure 6-5 ). theref ore , it is necessar y f or t0cki to be high f or at least 2t osc (and a small rc dela y of 20 ns) and lo w f or at least 2t osc (and a small rc dela y of 20 ns). ref er to the electr ical speci cation of the desired de vice . when a prescaler is used, the e xter nal cloc k input is divided b y the asynchronous r ipple-counter type pres- caler so that the prescaler output is symmetr ical. f or the e xter nal cloc k to meet the sampling requirement, the r ipple-counter m ust be tak en into account. there- f ore , it is necessar y f or t0cki to ha v e a per iod of at least 4t osc (and a small rc dela y of 40 ns) divided b y the prescaler v alue . the only requirement on t0cki high and lo w time is that the y do not violate the mini- m um pulse width requirement of 10 ns . ref er to par am- eters 40, 41 and 42 in the electr ical speci cation of the desired de vice . 6.2.2 tmr0 increment dela y since the prescaler output is synchroniz ed with the inter nal cloc ks , there is a small dela y from the time the e xter nal cloc k edge occurs to the time the timer0 mod- ule is actually incremented. figure 6-5 sho ws the dela y from the e xter nal cloc k edge to the timer incrementing. figure 6-5: timer0 timing with e xternal cloc k q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 exter nal cloc k input or prescaler output (2) exter nal cloc k/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling note 1: dela y from cloc k input change to timer0 increment is 3t osc to 7t osc. (dur ation of q = t osc). theref ore , the error in measur ing the inter v al betw een tw o edges on timer0 input = 4t osc max. 2: exter nal cloc k if no prescaler selected, prescaler output otherwise . 3: the arro ws indicate the points in time where sampling occurs . (3) (1)
pic16c71x ds30272a -page 34 1997 microchip technology inc. 6.3 pre scaler an 8-bit counter is a v ailab le as a prescaler f or the timer0 module , or as a postscaler f or the w atchdog timer , respectiv ely ( figure 6-6 ). f or simplicity , this counter is being ref erred to as ?rescaler throughout this data sheet. note that there is only one prescaler a v ailab le which is m utually e xclusiv ely shared betw een the timer0 module and the w atchdog timer . thus , a prescaler assignment f or the timer0 module means that there is no prescaler f or the w atchdog timer , and vice-v ersa. the psa and ps2:ps0 bits (option<3:0>) deter mine the prescaler assignment and prescale r atio . when assigned to the timer0 module , all instr uctions wr iting to the tmr0 register (e .g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler . when assigned to wdt , a clrwdt instr uction will clear the prescaler along with the w atchdog timer . the pres- caler is not readab le or wr itab le . note: wr iting to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, b ut will not change the prescaler assignment. figure 6-6: bloc k dia gra m of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clk out (=f osc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x w atchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs , t0se, psa, ps2:ps0 are (option<5:0>). psa wdt enab le bit m u x 0 1 0 1 data bus set ag bit t0if on ov er o w 8 psa t0cs
1997 microchip technology inc. ds30272a -page 35 pic16c71x 6.3.1 switching pre scaler assignment the prescaler assignment is fully under softw are con- trol, i.e ., it can be changed ?n the y dur ing prog r am e x ecution. note: t o a v oid an unintended de vice reset , the f ollo wing instr uction sequence (sho wn in example 6-1 ) m ust be e x ecuted when changing the prescaler assignment from timer0 to the wdt . this sequence m ust be f ollo w ed e v en if the wdt is disab led. example 6-1: c hangin g prescaler (timer0 ? wdt) bcf status, rp0 ;bank 0 c lrf tmr0 ;clear tmr0 & prescaler bsf status, rp0 ;bank 1 clrwdt ;clears wdt movlw b'xxxx1xxx' ;select s new prescale value movwf option_reg ; and assigns the prescaler to the w dt bcf status, rp0 ;bank 0 t o change prescaler from the wdt to the timer0 module use the sequence sho wn in example 6-2 . example 6-2: cha nging prescaler (wdt ? timer0) clrwdt ;clear wdt and prescaler b sf status, rp0 ;bank 1 m ovlw b'xxxx0xxx' ;select tmr0, new prescale value and m ovwf option_reg ;clock source bcf status, rp0 ;bank 0 t ab le 6-1: register s associated with timer0 ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 01h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 0bh,8bh, intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa por t a data direction register ---1 1111 ---1 1111 legend: x = unkno wn, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used b y timer0.
pic16c71x ds30272a -page 36 1997 microchip technology inc. no tes:
1997 microchip technology inc. ds30272a -page 37 pic16c71x figure 7-1: adcon0 register (ad dress 08 h ), pic16c710/71/711 r/w -0 r/w -0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 adcs1 ad cs0 (1) chs1 chs0 go/ done adif adon r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d con v ersion cloc k select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (cloc k der iv ed from an rc oscillation) bit 5: unimplemented: read as '0'. bit 4-3: chs1:chs0: analog channel select bits 00 = channel 0, (ra0/an0) 01 = channel 1, (ra1/an1) 10 = channel 2, (ra2/an2) 11 = channel 3, (ra3/an3) bit 2: go/ done : a/d con v ersion status bit if adon = 1 : 1 = a/d con v ersion in prog ress (setting this bit star ts the a/d con v ersion) 0 = a/d con v ersion not in prog ress (this bit is automatically cleared b y hardw are when the a/d con v er- sion is complete) bit 1: adif: a/d con v ersion complete interr upt flag bit 1 = con v ersion is complete (m ust be cleared in softw are) 0 = con v ersion is not complete bit 0: adon: a/d on bit 1 = a/d con v er ter module is oper ating 0 = a/d con v er ter module is shutoff and consumes no oper ating current note 1: bit5 of adcon0 is a gener al pur pose r/w bit f or the pic16c71 0/711 only . f or the pic16c 71 , this bit is unimplemented, read as '0'. 7.0 analog-to-digital con ver ter (a/d) module the analog-to-digital (a/d) con v er ter module has f our analog inputs . the a/d allo ws con v ersion of an analog input signal to a corresponding 8-bit digital n umber (ref er to applica- tion note an546 f or use of a/d con v er ter). the output of the sample and hold is the input into the con v er ter , which gener ates the result via successiv e appro xima- tion. the analog ref erence v oltage is softw are select- ab le to either the de vice s positiv e supply v oltage ( v dd ) or the v oltage le v el on the ra3/an3/ v ref pin. applicable devices 710 71 711 715 t he a/d con v er ter has a unique f eature of being ab le to oper ate while the de vice is in sleep mode . t o oper- ate in sleep , the a/d con v ersion cloc k m ust be der iv ed from the a/d s inter nal rc oscillator . the a/d module has three registers . these registers are: a/d result register ( adres) a/d control register 0 ( adcon0) a/d control register 1 ( adcon1) the adcon0 register , sho wn in figure 7-1 and figure 7-2 , controls the oper ation of the a/d module . the adcon1 register , sho wn in figure 7-3 con gures the functions of the por t pins . the por t pins can be con- gured as analog inputs (ra3 can also be a v oltage ref- erence) or as digital i/o .
pic16c71x ds30272a -page 38 1997 microchip technology inc. figure 7-2: adcon0 register (ad dress 1f h ), pic16c715 figure 7-3: adcon1 register , pic16c710/71/711 (ad dress 88 h ), pic16c715 (ad dress 9f h ) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 u-0 r/w -0 adcs1 adcs0 chs1 chs0 go/ done adon r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d con v ersion cloc k sele ct bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (cloc k der iv ed from an rc oscillation) bit 5: un used bit 6-3: chs1:chs0: analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 0, (ra0/an0) 101 = channel 1, (ra1/an1) 110 = channel 2, (ra2/an2) 111 = channel 3, (ra3/an3) bit 2: go/ done : a/d con v ersion st atus bit if adon = 1 1 = a/d con v e rsion in prog ress (setting this bit star ts the a/d con v ersion) 0 = a/d con v ersion not in prog ress (this bit is automatically cleared b y hardw are when the a/d con v er- sion is complete) bit 1: unimplemented: read as '0' bit 0: adon: a/d on bit 1 = a/d con v er ter module is oper ating 0 = a/d con v er ter module is shutoff and consumes no oper ating current u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 pcfg1 pcfg0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1-0: pcfg1:pcfg0 : a/d p or t con gur ation control bits a = analog input d = di g ital i/o pcfg1:pcfg0 ra1 & ra0 ra2 ra3 v ref 00 a a a v dd 01 a a v ref ra3 10 a d d v dd 11 d d d v dd
1997 microchip technology inc. ds30272a -page 39 pic16c71x the adres register contains the result of the a/d con- v ersion. when the a/d con v ersion is complete , the result is loaded into the adres register , the go/ done bit (adcon0<2>) is cleared, and a/d interr upt ag bit adif is set. the b loc k diag r am of the a/d module is sho wn in figure 7-4 . after the a/d module has been con gured as desired, the selected channel m ust be acquired bef ore the con- v ersion is star ted. the analog input channels m ust ha v e their corresponding tris bits selected as an input. t o deter mine acquisition t ime , see section 7.1 . after this acquisition time has elapsed the a/d con v er- sion can be star ted. the f ollo wing steps should be f ol- lo w ed f or doing an a/d con v ersion: 1. con gu re the a/d module: con gure analog pins / v oltage ref erence / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d con v ersion cloc k (adcon0) t ur n on a/d module (adcon0) 2. con gure a/d i nterr upt (if desired): clear adif bit set adie bit set gie bit 3. w ait the required acquisition time . 4. star t con v ersion: set go/ done bit (adcon0) 5. w ait f or a/d con v ersion to complete , b y either : p olling f or the go/ done bit to be cleared or w aiting f or the a/d interr upt 6. read a/d result register (adres), clear bit adif if required. 7. f or ne xt con v ersion, go to step 1 or step 2 as required. the a/d con v ersion time per bit is de ned as t ad . a minim um w ait of 2 t ad is required bef ore ne xt acquisition star ts . figure 7-4: a/d bloc k dia gram (input v oltage) v in v ref (ref erence v oltage) v dd pcfg 1 : pcfg 0 chs 1 : chs 0 00 or 10 or 11 01 ra 3/an3/v ref ra 0 /an 0 ra2/an2 ra1/an1 11 10 01 00 a/d con v er ter
pic16c71x ds30272a -page 40 1997 microchip technology inc. 7.1 a/d acquisition r equirements f or the a/d con v er ter to meet its speci ed accur acy , the charge holding capacitor ( c hold ) m ust be allo w ed to fully charge to the input channel v oltage le v el. the analog input model is sho wn in figure 7-5 . the source impedance ( r s ) and the inter nal sampling s witch ( r ss ) impedance directly aff ect the time required to charge the capacitor c hold . the sampling s witch ( r ss ) impedance v ar ies o v er the de vice v oltage ( v dd ), figure 7-5 . the source impedance aff ects the offset v oltage at the analog input (due to pin leakage current). t he maxim um recommended impedance f or ana- log sour ces is 10 k w . after the analog input channel is selected (changed) this acquisition m ust be done bef ore the con v ersion can be star ted. t o calculate the minim um acquisition time , equation 7- 1 ma y be used. this equation calculates the acquisition time to within 1 /2 lsb error is used (512 steps f or the a/d). the 1/2 lsb error is the maxim um error allo w ed f or the a/d to meet its speci ed accur acy . equation 7-1: a/d minim um char ging time v hold = ( v ref - ( v ref /512)) ?(1 - e (- t cap / c hold ( r ic + r ss + r s )) ) giv en: v hold = ( v ref /512), f or 1/2 lsb resolution the abo v e equation reduces to: t cap = - (51.2 pf)(1 k w + r ss + r s ) ln(1/51 1) example 7-1 sho ws the calculation of the minim um required acquisition time t acq . this calculation is based on the f ollo wing system assumptions . c hold = 51.2 pf r s = 10 k w 1/2 lsb error v dd = 5v ? rss = 7 k w t emp ( application system max.) = 50 c v hold = 0 @ t = 0 example 7-1: calculating the m inim um required aquisition t ime t acq = ampli er settling time + holding capacitor charging time + t emper ature coef cient t acq = 5 m s + t c ap + [(t emp - 25 c)(0.05 m s/ c)] t c ap = - c hold ( r ic + r ss + r s ) ln(1/51 1) -51.2 pf (1 k w + 7 k w + 10 k w ) ln(0.0020) -51.2 pf (18 k w ) ln(0.0020) -0.921 m s (-6. 2364) 5.7 47 m s t acq = 5 m s + 5.7 47 m s + [(50 c - 25 c)(0.05 m s/ c)] 10. 7 47 m s + 1.25 m s 11. 9 97 m s note 1: the ref erence v oltage (v ref ) has no eff ect on the equation, since it cancels itself out. note 2: the charge holding capacitor (c hold ) is not discharged after each con v ersion. note 3: the maxim um recommended impedance f or analog sources is 10 k w . this is required to meet the pin leakage speci - cation. note 4: after a c on v ersion has completed, a 2.0 t ad dela y m ust complete bef ore acqui- sition can begin again. dur ing this time the holding capacitor is not connected to the selected a/d input channel. figure 7-5: analog inp ut model c pin v a rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = d a c capacitance v ss 6v sampling switch 5v 4 v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold v oltage = leakage current at the pin due to = interconnect resistance = sampling s witch = sample/hold capacitance (from d a c) v ar ious junctions
1997 microchip technology inc. ds30272a -page 41 pic16c71x 7.2 selecting the a /d con ver sion cloc k the a/d con v ersion time per bit is de ned as t ad . the a/d con v ersion requires 9.5 t ad per 8-bit con v ersion. t he source of the a/d con v ersion cloc k is softw are select ab le . the f our possib le options f or t ad are: 2 t osc 8 t osc 32 t osc inter nal rc oscillator f or correct a/d con v ersions , the a/d con v ersion cloc k ( t ad ) m ust be selected to ensure a minim um t ad time of: 2.0 m s f or the pic16c71 1.6 m s f or all other pic16c71x de vices t ab le 7-1 and t ab le 7-2 and s ho w the resultant t ad times der iv ed from the de vice oper ating frequencies and the a/d cloc k source selected. 7.3 conf iguring analog p or t pins the adcon1 and trisa registers control the oper a- tion of the a/d por t pins . the por t pins that are desired as analog inputs m ust ha v e their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output le v el ( v oh or v ol ) will be con v er ted. the a/d oper ation is independent of the state of the chs2:chs0 bits and the tris bits . note 1: when reading the por t register , all pins con gured as analog input channel s will read as cleared (a lo w le v el). pins con g- ured as digital inputs , will con v er t an ana- log input. analog le v els on a digitally con gured input will not aff ect the con v er- sion accur acy . note 2: analog le v els on an y pin that is de ned as a digital input (including the an7:an0 pins), ma y cause the input b uff er to con- sume current that is out of the de vices speci cation. t ab le 7-1: t ad vs . de vice operating frequencies, pic16c71 t ab le 7-2: t ad vs . de vice operating frequencies, p ic16c710/711, pic16c715 ad cloc k sour ce ( t ad ) de vice frequenc y operation adcs1:adcs0 20 mhz 16 mhz 4 mhz 1 mhz 333.33 khz 2 t osc 00 100 ns (2) 125 ns (2) 500 ns (2) 2.0 m s 6 m s 8 t osc 01 400 ns (2) 500 ns (2) 2.0 m s 8.0 m s 24 m s (3) 32 t osc 10 1.6 m s (2) 2.0 m s 8.0 m s 32.0 m s (3) 96 m s (3) rc (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) 2 - 6 m s (1) legend: shaded cells are outside of recommended r ange . note 1: the rc source has a typical t ad time of 4 m s . 2: these v alues violate the minim um required t ad time . 3: f or f aster con v ersion times , the selection of another cloc k source is recommended. 4: when d e vice frequency is g reater than 1 mhz, the rc a/d c on v ersion cloc k source is recommended f or sleep oper ation only . 5: f or e xtended v oltage de vices (lc), please ref er to electr ical speci cations section. ad cloc k sour ce ( t ad ) de vice frequenc y operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2 t osc 00 100 ns (2) 400 ns (2) 1.6 m s 6 m s 8 t osc 01 400 ns (2) 1.6 m s 6.4 m s 24 m s (3) 32 t osc 10 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) rc (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) legend: shaded cells are outside of recommended r ange . note 1: t he rc source has a typical t ad time of 4 m s . 2: these v alues violate the minim um required t ad time . 3: f or f aster con v ersion times , the selection of another cloc k source is recommended . 4: when de vice frequency is g reater than 1 mhz, the rc a/d con v ersion cloc k source is recommended f or sleep oper ation only . 5: f or e xtended v oltage de vices (lc), please ref er to electr ical speci cations section.
pic16c71x ds30272a -page 42 1997 microchip technology inc. 7.4 a/d con ver sions example 7-2 sho ws ho w to perf or m an a/d con v ersion. the ra pins are con gured as analog inputs . the ana- log ref erence ( v ref ) is the de vice v dd . the a/d inter- r upt is enab led, and the a/d con v ersion cloc k is f rc . the con v ersion is perf or med on the ra0 pin ( channel 0) . clear ing the go/ done bit dur ing a con v ersion will abor t the current con v ersion. the adres register will no t be updated with the par tially completed a/d con- v ersion sample . that is , the adres register will con- tin ue to contain the v alue of the last completed con v ersion (or the last v alue wr itten to the adres reg- ister). after the a/d con v ersion is abor ted, a 2 t ad w ait is required bef ore the ne xt acquisition is star ted. after this 2 t ad w ait, an acquisition is automatically star ted on the selected channel. note: the go/ done bit should no t be set in the same instr uction that tur ns on the a/d . example 7-2: a / d con ver sion bsf status, rp0 ; select bank 1 clrf adcon1 ; configure a/d inputs bcf status, rp0 ; select bank 0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bsf intcon, adie ; enable a/d interrupt bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input channel has elapsed. ; then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the a/d conversion.
1997 microchip technology inc. ds30272a -page 43 pic16c71x 7.4.1 f aster con v ersion - lo w er resolution t r ade-off not all applications require a result with 8-bits of reso- lution, b ut ma y instead require a f aster con v ersion time . the a/d module allo ws users to mak e the tr ade-off of con v ersion speed to resolution. regardless of the res- olution required, the acquisition time is the same . t o speed up the con v ersion, the cloc k source of the a/d module ma y be s witched so that the t ad time violates the minim um speci ed time (see the applicab le electr i- cal speci cation). once the t ad time violates the mini- m um speci ed time , all the f ollo wing a/d result bits are not v alid (see a/d con v ersion timing in the electr ical speci cations section.) the cloc k sources ma y only be s witched betw een the three oscillator v ersions (cannot be s witched from/to rc). the equation to deter mine the time bef ore the oscillator can be s witched is as f ollo ws: con v ersion time = 2 t ad + n ? t ad + (8 - n)(2 t osc ) where: n = n umber of bits of resolution required. since the t ad is based from the de vice oscillator , the user m ust use some method (a timer , softw are loop , etc.) to deter mine when the a/d oscillator ma y be changed. example 7-3 sho ws a compar ison of time required f or a con v ersion with 4-bits of resolution, v er- sus the 8-bit resolution con v ersion. the e xample is f or de vices oper ating at 20 mhz and 16 mhz (the a/d cloc k is prog r ammed f or 32 t osc ), and assumes that immediately after 6 t ad , the a/d cloc k is prog r ammed f or 2 t osc . the 2 t osc violates the minim um t ad time since the last 4-bits will not be con v er ted to correct v alues . example 7-3: 4-bit vs . 8-bit con ver sion times freq. (mhz) (1) resolution 4-bit 8-bit t ad 20 1.6 m s 1.6 m s 16 2.0 m s 2.0 m s t osc 20 50 ns 50 ns 16 62.5 ns 62.5 ns 2 t ad + n ? t ad + (8 - n)(2 t osc ) 20 10 m s 16 m s 16 12.5 m s 20 m s note 1: the pic16c71 has a minim um t ad time of 2.0 m s . all other pic16c71x de vices ha v e a minim um t ad time of 1.6 m s .
pic16c71x ds30272a -page 44 1997 microchip technology inc. 7.5 a/d operation during sleep the a/d module can oper ate dur ing sleep mode . this requires that the a/d cloc k source be set to rc (adcs1:adcs0 = 11 ). when the rc cloc k source is selected, the a/d module w aits one instr uction cycle bef ore star ting the con v ersion. this allo ws the sleep instr uction to be e x ecuted, which eliminates all digital s witching noise from the con v ersion. when the con v er- sion is completed the go/ done bit will be cleared, and the result loaded into the adres register . if the a/d interr upt is enab led, the de vice will w ak e-up from sleep . if the a/d interr upt is not enab led, the a/d mod- ule will then be tur ned off , although the adon bit will remain set. when the a/d cloc k source is another cloc k option (not rc), a sleep instr uction will cause the present con v er- sion to be abor ted and the a/d module to be tur ned off , though the adon bit will remain set. t ur ning off the a/d places the a/d module in its lo w est current consumption state . 7.6 a/d accurac y/err or the absolute accur acy speci ed f or the a/d con v er ter includes the sum of all contr ib utions f or quantization error , integ r al error , diff erential error , full scale error , off- set error , and monotonicity . it is de ned as the maxi- m um de viation from an actual tr ansition v ersus an ideal tr ansition f or an y code . the absolute error of the a/d con v er ter is speci ed at < 1 lsb f or v dd = v ref (o v er the de vice s speci ed oper ating r ange). ho w e v er , the accur acy of the a/d con v er ter will deg r ade as v dd div erges from v ref . f or a giv en r ange of analog inputs , the output digital code will be the same . this is due to the quantization of the analog input to a digital code . quantization error is typically 1/2 lsb and is inherent in the analog to dig- ital con v ersion process . the only w a y to reduce quanti- zation error is to increase the resolution of the a/d con v er ter . offset error measures the rst actual tr ansition of a code v ersus the rst ideal tr ansition of a code . offset error shifts the entire tr ansf er function. offset error can be calibr ated out of a system or introduced into a sys- tem through the inter action of the total leakage current and source impedance at the analog input. gain error measures the maxim um de viation of the last actual tr ansition and the last ideal tr ansition adjusted f or offset error . this error appears as a change in slope of the tr ansf er function. the diff erence in gain error to note: f or the a/d module to oper ate in sleep , the a/d cloc k source m ust be set to rc (adcs1:adcs0 = 11 ). t o perf or m an a/d con v ersion in sleep , ensure the sleep instr uction immediately f ollo ws the instr uc- tion that sets the go/ done bit. full scale error is that full scale does not tak e offset error into account. gain error can be calibr ated out in soft- w are . linear ity error ref ers to the unif or mity of the code changes . linear ity errors cannot be calibr ated out of the system. integ r al non-linear ity error measures the actual code tr ansition v ersus the ideal code tr ansition adjusted b y the gain error f or each code . diff erential non-linear ity measures the maxim um actual code width v ersus the ideal code width. this measure is unadjusted. i n systems where the de vice frequency is lo w , use of the a/d rc cloc k is pref erred. at moder ate to high fre- quencies , t ad should be der iv ed from the de vice oscil- lator . t ad m ust not violate the minim um and should be 8 m s f or pref erred oper ation. this is because t ad , when der iv ed from t osc , is k ept a w a y from on-chip phase cloc k tr ansitions . this reduces , to a large e xtent, the eff ects of digital s witching noise . this is not possib le with the rc der iv ed cloc k. the loss of accur acy due to digital s witching noise can be signi cant if man y i/o pins are activ e . in systems where the de vice will enter sleep mode after the star t of the a/d con v ersion, the rc cloc k source selection is required. in this mode , the digital noise from the modules in sleep are stopped. this method giv es high accur acy . 7.7 eff ect s of a reset a de vice reset f orces all registers to their reset state . this f orces the a/d module to be tur ned off , and an y con v ersion is abor ted . t he v alue that is in the adres register is not modi ed f or a p o w er-on reset. the adres register will contain unkno wn data after a p o w er-on reset. 7.8 connection considerations if the input v oltage e xceeds the r ail v alues ( v ss or v dd ) b y g reater than 0.2v , then the accur acy of the con v er- sion is out of speci cation. an e xter nal rc lter is sometimes added f or anti-alias- ing of the input signal. the r component should be selected to ensure that the total source impedance is k ept under the 10 k w recommended speci cation. an y e xter nal components connected (via hi-impedance) to an analog input pin (capacitor , z ener diode , etc.) should ha v e v er y little leakage current at the pin. note: care m ust be tak en when using the ra0 pin in a/d con v ersions due to its pro ximity to the osc1 pin.
1997 microchip technology inc. ds30272a -page 45 pic16c71x 7.9 t ransf er function the ideal tr ansf er function of the a/d con v er ter is as f ol- lo ws: the rst tr ansition occurs when the analog input v oltage ( v ain ) is a nalog v ref /2 56 ( figure 7-6 ). 7.10 ref erences a v er y good ref erence f or understanding a/d con v er t- ers is the "analog-digital con v ersion handbook" third edition, pub lished b y prentice hall (isbn 0-13-03- 2848-0). figure 7-6: a/d t ransf er function digital code output ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb (full scale) analog input v oltage figure 7-7: flo wc ha r t of a/d operation acquire adon = 0 adon = 0? go = 0? a/d cloc k go = 0 adif = 0 abor t con v ersion sleep p o w er -d o wn a/d w ait 2 t ad w ak e-up y es no y es no no y es finish con v ersion go = 0 adif = 1 de vice in no y es finish con v ersion go = 0 adif = 1 w ait 2 t ad sta y in sleep selected channel = rc? sleep no y es instr uction? star t of a/d con v ersion dela y ed 1 instr uction cycle f rom sleep? p o w er - do wn a/d y es no w ait 2 t ad finish con v ersion go = 0 adif = 1 sleep ?
pic16c71x ds30272a -page 46 1997 microchip technology inc. t ab le 7-3: register s/bits associated with a /d , pic16c710/71/711 t ab le 7-4: register s/bits associated with a/d , pic16c715 ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh,8bh intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 89h adres a/d result register xxxx xxxx uuuu uuuu 08h adcon0 adcs1 adcs0 chs1 chs0 go/ done adif adon 00-0 0000 00-0 0000 88h adcon1 pcfg1 pcfg0 ---- --00 ---- --00 05h por t a ra4 ra3 ra2 ra1 ra0 ---x 0000 ---u 0000 85h trisa por t a data direction register ---1 1111 ---1 1111 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used f or a/d con v ersion. ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on: por, bor v alue on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif -0-- ---- -0-- ---- 8ch pie1 adie -0-- ---- -0-- ---- 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon 0 adcs 1 adcs 0 chs2 chs1 chs0 go/ done adon 0000 00-0 0000 00-0 9fh adcon 1 pcfg1 pcfg0 ---- --00 ---- --00 05h por t a ra4 ra3 ra2 ra1 ra0 ---x 0000 ---u 0000 85h trisa trisa4 trisa 3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0'. shaded cells are not used f or a/d con v ersion.
1997 microchip technology inc. ds30272a -page 47 pic16c71x 8.0 special features of the cpu what sets a microcontroller apar t from other proces- sors are special circuits to deal with the needs of real- time applications . the pic16cxx f amily has a host of such f eatures intended to maximiz e system reliability , minimiz e cost through elimination of e xter nal compo- nents , pro vide po w er sa ving oper ating modes and off er code protection. these are: oscillator selection reset - p o w er-on reset (por) - p o w er-up timer (pwr t) - oscillator star t-up timer (ost) - bro wn-out reset (bor) (pic16c710/711/715) - p ar ity error reset (per) (pic16c715) interr upts w atchdog timer (wdt) sleep code protection id locations in-circuit ser ial prog r amming the pic16cxx has a w atchdog timer which can be shut off only through con gur ation bits . it r uns off its o wn rc oscillator f or added reliability . there are tw o timers that off er necessar y dela ys on po w er-up . one is the oscillator star t-up timer (ost), intended to k eep the chip in reset until the cr ystal oscillator is stab le . the other is the p o w er-up timer (pwr t), which pro vides a applicable devices 710 71 711 715 x ed dela y of 72 ms (nominal) on po w er-up only , designed to k eep the par t in reset while the po w er sup- ply stabiliz es . with these tw o timers on-chip , most applications need no e xter nal reset circuitr y . sleep mode is designed to off er a v er y lo w current po w er-do wn mode . the user can w ak e-up from sleep through e xter nal reset, w atchdog timer w ak e-up , or through an interr upt. se v er al oscillator options are also made a v ailab le to allo w the par t to t the application. the rc oscillator option sa v es system cost while the lp cr ystal option sa v es po w er . a set of con gur ation bits are used to select v ar ious options . 8.1 c on guration bits the con gur ation bits can be prog r ammed (read as '0') or left unprog r ammed (read as '1') to select v ar ious de vice con gur ations . these bits are mapped in pro- g r am memor y location 2007h. the user will note that address 2007h is be y ond the user prog r am memor y space . in f act, it belongs to the special test/con gur ation memor y space (2000h - 3fffh), which can be accessed only dur ing prog r am- ming. figure 8-1: configuration w or d f or pi c16c 71 cp0 pwr te wdte fosc1 fosc0 register : config address 2007h bit13 bit0 bit 13-5: unimplemented: read as '1' bit 4: cp0: code protection bit 1 = code protection off 0 = all memor y is code protected, b ut 00h - 3fh is wr itab le bit 3: pwr te : p o w er-up timer enab le bit 1 = p o w er-up timer enab led 0 = p o w er-up timer disab led bit 2: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 1-0: fosc1:fosc0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator
pic16c71x ds30272a -page 48 1997 microchip technology inc. figure 8-2: configuration w or d, pic16c710/711 figure 8-3: configuration w or d, pic16c715 cp0 cp0 cp0 cp0 cp0 cp0 cp0 bo den cp0 cp0 pwr te wdte fosc1 fosc0 register : config address 2007h bit13 bit0 bit 13-7 cp0: code protection bits (2) 5-4: 1 = code protection off 0 = all memor y is code protected, b ut 00h - 3fh is wr itab le bit 6: boden : bro wn-out reset enab le bit (1) 1 = bor enab led 0 = bor disab led bit 3: pwr te : p o w er-up timer enab le bit (1) 1 = pwr t disab led 0 = pwr t enab led bit 2: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 1-0: fosc1:fosc0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enab ling bro wn-out reset automatically enab les p o w er-up timer (pwr t) regardless of the v alue of bit pwr te . ensure the p o w er-up timer is enab led an ytime bro wn-out reset is enab led. 2: all of the cp0 bits ha v e to be giv en the same v alue to enab le the code protection scheme listed. cp1 cp0 cp1 cp0 cp1 cp0 mpeen boden cp1 cp0 pwr te wdte fosc1 fosc0 register : config address 2007h bit13 bit0 bit 13-8 cp1:cp0: code protection bits (2) 5-4: 11 = code protection off 10 = upper half of prog r am memor y code protected 01 = upper 3/4th of prog r am memor y code protected 00 = all memor y is code protected bit 7: mpeen : memor y p ar ity error enab le 1 = memor y p ar ity chec king is enab led 0 = memor y p ar ity chec king is disab led bit 6: boden : bro wn-out reset enab le bit (1) 1 = bor enab led 0 = bor disab led bit 3: pwr te : p o w er-up timer enab le bit (1) 1 = pwr t disab led 0 = pwr t enab led bit 2: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 1-0: fosc1:fosc0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enab ling bro wn-out reset automatically enab les p o w er-up timer (pwr t) regardless of the v alue of bit pwr te . ensure the p o w er-up timer is enab led an ytime bro wn-out reset is enab led. 2: all of the cp1:cp0 pairs ha v e to be giv en the same v alue to enab le the code protection scheme listed.
1997 microchip technology inc. ds30272a -page 49 pic16c71x 8.2 oscillator con gurations 8.2.1 oscillator t ypes the pic16cxx can be oper ated in f our diff erent oscil- lator modes . the user can prog r am tw o con gur ation bits (fosc1 and fosc0) to select one of these f our modes: lp lo w p o w er cr ystal xt cr ystal/resonator hs high speed cr ystal/resonator rc resistor/capacitor 8.2.2 cr ystal oscillator/ceramic resonators in xt , lp or hs modes a cr ystal or cer amic resonator is connected to the osc1/clkin and osc2/clk out pins to estab lish oscillation ( figure 8-4 ). the pic16cxx oscillator design requires the use of a par- allel cut cr ystal. use of a ser ies cut cr ystal ma y giv e a frequency out of the cr ystal man uf acturers speci ca- tions . when in xt , lp or hs modes , the de vice can ha v e an e xter nal cloc k source to dr iv e the osc1/ clkin pin ( figure 8-5 ). figure 8-4: cr ystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 8-5: external cloc k input operation (hs, xt or lp osc configuration) c1 c 2 xt al osc2 note1 osc1 r f sleep pic16cxxx rs see t ab le 8-1 and t ab le 8-1 f or recommended v alues of c1 and c2. note 1: a ser ies resistor ma y be required f or a t str ip cut cr ystals . 2: the b uff er is on the osc2 pin. (2) t o inter nal logic osc1 osc2 open cloc k from e xt. system pic16cxxx t ab le 8-1: ceramic resonator s, pic16c71 t ab le 8-2: capacitor selection for cr ystal oscillator , pic16c71 rang es t ested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 47 - 100 pf 15 - 68 pf 15 - 68 pf 47 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 15 - 68 pf 10 - 47 pf 15 - 68 pf 10 - 47 pf these v alues are f or design guidance onl y . see notes at bottom of page . resonator s used: 455 khz p anasonic efo-a455k04b 0.3% 2.0 mhz mur ata er ie csa2.00mg 0.5% 4.0 mhz mur ata er ie csa4.00mg 0.5% 8.0 mhz mur ata er ie csa8.00mt 0.5% 16.0 mhz mur ata er ie csa16.00mx 0.5% all resonators used did not ha v e b uilt-in capacitors . mode freq osc1 osc2 lp 32 khz 200 khz 33 - 68 pf 15 - 47 pf 33 - 68 pf 15 - 47 pf xt 100 khz 500 khz 1 mhz 2 mhz 4 mhz 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf hs 8 mhz 20 mhz 15 - 47 pf 15 - 47 pf 15 - 47 pf 15 - 47 pf these v alues are f or design guidance onl y . see notes at bottom of page .
pic16c71x ds30272a -page 50 1997 microchip technology inc. t ab le 8-3: ceramic resonator s, pic16c710/711/715 rang es t ested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these v alues are f or design guidance onl y . see notes at bottom of page . resonator s used: 455 khz p anasonic efo-a455k04b 0.3% 2.0 mhz mur ata er ie csa2.00mg 0.5% 4.0 mhz mur ata er ie csa4.00mg 0.5% 8.0 mhz mur ata er ie csa8.00mt 0.5% 16.0 mhz mur ata er ie csa16.00mx 0.5% all resonators used did not ha v e b uilt-in capacitors . t ab le 8-4: capacitor selection f or cr ystal oscillator , pic16c710/711/715 osc t ype cr ystal freq cap. rang e c1 cap. rang e c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these v alues are f or design guidance onl y . see notes at bottom of page . cr ystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended v alues of c1 and c2 are identical to the r anges tested tab le . 2: higher capacitance increases the stability of oscillator b ut also increases the star t-up time . 3: since each resonator/cr ystal has its o wn char acter istics , the user should consult the resonator/cr ystal man- uf acturer f or appropr iate v alues of e xter nal components . 4: rs ma y be required in hs mode as w ell as xt mode to a v oid o v erdr iving cr ystals with lo w dr iv e le v el speci- cation.
1997 microchip technology inc. ds30272a -page 51 pic16c71x 8.2.3 exter nal cr ystal oscillator circuit either a prepac kaged oscillator can be used or a simple oscillator circuit with ttl gates can be b uilt. prepac k- aged oscillators pro vide a wide oper ating r ange and better stability . a w ell-designed cr ystal oscillator will pro vide good perf or mance with ttl gates . t w o types of cr ystal oscillator circuits can be used; one with ser ies resonance , or one with par allel resonance . figure 8-6 sho ws implementation of a par allel resonant oscillator circuit. the circuit is designed to use the fun- damental frequency of the cr ystal. the 74as04 in v er ter perf or ms the 180-deg ree phase shift that a par allel oscillator requires . the 4.7 k w resistor pro vides the negativ e f eedbac k f or stability . the 10 k w potentiome- ter biases the 74as04 in the linear region. this could be used f or e xter nal oscillator designs . figure 8-6: external p arallel resonant cr ystal oscillator cir cuit figure 8-7 sho ws a ser ies resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the cr ystal. the in v er ter perf or ms a 180- deg ree phase shift in a ser ies resonant oscillator cir- cuit. the 330 k w resistors pro vide the negativ e f eed- bac k to bias the in v er ters in their linear region. figure 8-7: external series resonant cr ystal oscillator cir cuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xt al 10k 74as04 clkin t o other de vices pic16cxxx 330 k w 74as04 74as04 pic16cxxx clkin t o other de vices xt al 330 k w 74as04 0.1 m f 8.2.4 rc oscillator f or timing insensitiv e applications the ?c de vice option off ers additional cost sa vings . the rc oscillator frequency is a function of the supply v oltage , the resis- tor (re xt) and capacitor (ce xt) v alues , and the oper at- ing temper ature . in addition to this , the oscillator frequency will v ar y from unit to unit due to nor mal pro- cess par ameter v ar iation. fur ther more , the diff erence in lead fr ame capacitance betw een pac kage types will also aff ect the oscillation frequency , especially f or lo w ce xt v alues . the user also needs to tak e into account v ar iation due to toler ance of e xter nal r and c compo- nents used. figure 8-8 sho ws ho w the r/c combina- tion is connected to the pic16cxx. f or re xt v alues belo w 2.2 k w , the oscillator oper ation ma y become unstab le , or stop completely . f or v er y high re xt v alues (e .g. 1 m w ), the oscillator becomes sensitiv e to noise , humidity and leakage . thus , w e recommend to k eep re xt betw een 3 k w and 100 k w . although the oscillator will oper ate with no e xter nal capacitor (ce xt = 0 pf), w e recommend using v alues abo v e 20 pf f or noise and stability reasons . with no or small e xter nal capacitance , the oscillation frequency can v ar y dr amatically due to changes in e xter nal capacitances , such as pcb tr ace capacitance or pac k- age lead fr ame capacitance . see char acter ization data f or desired de vice f or rc fre- quency v ar iation from par t to par t due to nor mal pro- cess v ar iation. the v ar iation is larger f or larger r (since leakage current v ar iation will aff ect rc frequency more f or large r) and f or smaller c (since v ar iation of input capacitance will aff ect rc frequency more). see char acter ization data f or desired de vice f or v ar ia- tion of oscillator frequency due to v dd f or giv en re xt/ ce xt v alues as w ell as frequency v ar iation due to oper- ating temper ature f or giv en r, c , and v dd v alues . the oscillator frequency , divided b y 4, is a v ailab le on the osc2/clk out pin, and can be used f or test pur- poses or to synchroniz e other logic (see figure 3-2 f or w a v ef or m). figure 8-8: rc oscillator mode osc2/clkout cext v dd rext v ss pic16cxxx osc1 fosc/4 internal clock
pic16c71x ds30272a -page 52 1997 microchip technology inc. 8.3 reset the pic16cxx diff erentiates betw een v ar ious kinds of reset: p o w er-on reset (por) mclr reset dur ing nor mal oper ation mclr reset dur ing sleep wdt reset (nor mal oper ation) bro wn-out reset (bor) (pic16c710/711/715) p ar ity error reset (pic16c715) some registers are not aff ected in an y reset condition; their status is unkno wn on por and unchanged in an y other reset. most other registers are reset to a ?eset state on p o w er-on reset (por), on the mclr and applicable devices 710 71 711 715 wdt reset, on mclr reset dur ing sleep , and bro wn- out reset (bor). the y are not aff ected b y a wdt w ak e-up , which is vie w ed as the resumption of nor mal oper ation. the t o and pd bits are set or cleared diff er- ently in diff erent reset situations as indicated in t ab le 8- 7 , t ab le 8-8 and t ab le 8-9 . these bits are used in soft- w are to deter mine the nature of the reset. see t ab le 8- 10 and t ab le 8-11 f or a full descr iption of reset states of all registers . a simpli ed b loc k diag r am of the on-chip reset circuit is sho wn in figure 8-9 . the pic16c710/711/715 ha v e a mclr noise lter in the mclr reset path. the lter will detect and ignore small pulses . it should be noted that a wdt reset does not dr iv e mclr pin lo w . figure 8-9: simplified bloc k dia gram of on-c hip reset cir cuit s r q exter nal reset mclr /v pp pin v dd osc1/ wdt module v dd r ise detect ost/pwr t on-chip (1) rc osc wdt time-out p o w er-on reset ost pwr t chip_reset 10 -b it ripple-counter enab le ost enab le pwr t sleep see t ab le 8-6 f or time-out situations . note 1: this is a separ ate oscillator from the rc oscillator of the clkin pin. 2: bro wn-out reset is implemented on the pic16c710/711/715. 3: p ar ity error reset is implemented on the pic16c715. bro wn-out reset (2) boden clkin pin 10-bit ripple -c ounter prog r am memor y p ar ity (3) mpeen
1997 microchip technology inc. ds30272a -page 53 pic16c71x 8.4 p o wer -on reset (por), p o wer -up timer (pwr t) and oscillator star t-up timer (ost), and br o w n-out reset (bor) 8.4.1 p o w er-on reset (por) a p o w er-on reset pulse is gener ated on-chip when v dd r ise is detected (in the r ange of 1.5 v - 2.1v). t o tak e adv antage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will eliminate e xter nal rc components usually needed to create a p o w er-on reset. a maxim um r ise time f or v dd is spec- i ed. see electr ical speci cations f or details . when the de vice star ts nor mal oper ation (e xits the reset condition), de vice oper ating par ameters (v oltage , frequency , temper ature , ...) m ust be met to ensure oper ation. if these conditions are not met, the de vice m ust be held in reset until the oper ating conditions are met. bro wn-out reset ma y be used to meet the star tup conditions . f or additional inf or mation, ref er to application note an607, " p o w e r-up t roub le shooting ." 8.4.2 p o w er-up timer (pwr t) the p o w er-up timer pro vides a x ed 72 ms nominal time-out on po w er-up only , from the por. the p o w er- up timer oper ates on an inter nal rc oscillator . the chip is k ept in reset as long as the pwr t is activ e . the pwr t s time dela y allo ws v dd to r ise to an acceptab le le v el. a con gur ation bit is pro vided to enab le/disab le the pwr t . applicable devices 710 71 711 715 applicable devices 710 71 711 715 the po w er-up time dela y will v ar y from chip to chip due to v dd , temper ature , and process v ar iation. see dc par ameters f or details . 8.4.3 oscillator star t-up timer (ost) the oscillator star t-up timer (ost) pro vides 1024 oscillator cycle (from osc1 input) dela y after the pwr t dela y is o v er . this ensures that the cr ystal oscil- lator or resonator has star ted and stabiliz ed. the ost time-out is in v ok ed only f or xt , lp and hs modes and only on p o w er-on reset or w ak e-up from sleep . 8.4.4 bro wn-out reset (bor) a con gur ation bit, boden, can disab le (if clear/pro- g r ammed) or enab le (if set) the bro wn-out reset cir- cuitr y . if v dd f alls belo w 4.0v (3.8v - 4.2v r ange) f or g reater than par ameter #35, the bro wn-out situation will reset the chip . a reset ma y not occur if v dd f alls belo w 4.0v f or less than par ameter #35. the chip will remain in bro wn-out reset until v dd r ises abo v e bv dd . the p o w er-up timer will no w be in v ok ed and will k eep the chip in reset an additional 72 ms . if v dd drops belo w bv dd while the p o w er-up timer is r unning, the chip will go bac k into a bro wn-out reset and the p o w er-up timer will be initializ ed. once v dd r ises abo v e bv dd , the p o w er-up timer will e x ecute a 72 ms time dela y . the p o w er-up timer should alw a ys be enab led when bro wn-out reset is enab led. figure 8-10 sho ws typical bro wn-out situations . applicable devices 710 71 711 715 applicable devices 710 71 711 715 figure 8-10: br o wn-out sit uations 72 ms bv dd v dd inter nal reset bv dd v dd inter nal reset 72 ms <72 ms 72 ms bv dd v dd inter nal reset
pic16c71x ds30272a -page 54 1997 microchip technology inc. 8.4.5 time-out sequence on po w er-up the time-out sequence is as f ollo ws: first pwr t time-out is in v ok ed after the por time dela y has e xpired. then ost is activ ated. the total time-out will v ar y based on oscillator con gur ation and the status of the pwr t . f or e xample , in rc mode with the pwr t disab led, there will be no time-out at all. figure 8-11 , figure 8-12 , and figure 8-13 depict time-out sequences on po w er-up . since the time-outs occur from the por pulse , if mclr is k ept lo w long enough, the time-outs will e xpire . then br inging mclr high will begin e x ecution immediately ( figure 8-12 ). this is useful f or testing pur poses or to synchroniz e more than one pic16cxx de vice oper at- ing in par allel. t ab le 8-10 and t ab le 8-11 sho w the reset conditions f or some special function registers , while t ab le 8-12 and t ab le 8-13 sho w the reset conditions f or all the registers . 8.4.6 p o w er control/status register (pcon) the p o w er control/status register , pcon has up to tw o b its , depending upon the de vice . bit0 is bro wn-out reset status bit, bor . bit bor is unkno wn o n a p o w er-on reset. it m ust then be set b y the user and chec k ed on subsequent resets to see if bit bor cleared, indicating a bor occurred. the bor bit is a "don? care" bit and is not necessar ily predictab le if the bro wn-out reset circuitr y is disab led (b y clear ing bit boden in the con gur ation w ord). applicable devices 710 71 711 715 applicable devices 710 71 711 715 bit1 is por ( p o w er-on reset status bit ) . it is cleared on a p o w er-on reset and unaff ected otherwise . the user m ust set this bit f ollo wing a p o w er-on reset. f or the pic16c715, bit2 is per (p ar ity error reset). it is cleared on a p ar ity error reset and m ust be set b y user softw are . it will also be set on a p o w er-on reset. f or the pic16c715, bit7 is mpeen (memor y p ar ity error enab le). this bit re ects the status of the mpeen bit in con gur ation w ord. it is unaff ected b y an y reset of interr upt. 8.4.7 p ar ity error reset (per) the pic16c715 has on-chip par ity bits that can be used to v er ify the contents of prog r am memor y . p ar ity bits ma y be useful in applications in order to increase o v er all reliability of a system. there are tw o par ity bits f or each w ord of prog r am memor y . the par ity bits are computed on alter nating bits of the prog r am w ord. one computation is per- f or med using e v en par ity , the other using odd par ity . as a prog r am e x ecutes , the par ity is v er i ed. the e v en par- ity bit is xor d with the e v en bits in the prog r am mem- or y w ord. the odd par ity bit is negated and xor d with the odd bits in the prog r am memor y w ord. when an error is detected, a reset is gener ated and the per ag bit 2 in the pcon register is cleared (logic ??. this indi- cation can allo w softw are to act on a f ailure . ho w e v er , there is no indication of the prog r am memor y location of the f ailure in prog r am memor y . this ag can only be set (logic ?? b y softw are . the par ity arr a y is user selectab le dur ing prog r amming. bit 7 of the con gur ation w ord located at address 2007h can be prog r ammed (read as ?? to disab le par- ity . if left unprog r ammed (read as ??, par ity is enab led. applicable devices 710 71 711 715 t ab le 8-5: time-out in v arious situations, pic16c71 t ab le 8-6: time-out in v arious situations, pic16c710/711 /715 oscillator con guration p o wer -up w ake-up fr om sleep pwr te = 1 pwr te = 0 xt , hs , lp 72 ms + 1024 t osc 1024 t osc 1024 t osc rc 72 ms oscillator con guration p o wer -up br o wn-out w ake-up fr om sleep pwr te = 0 pwr te = 1 xt , hs , lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024t osc 1024 t osc rc 72 ms 72 ms
1997 microchip technology inc. ds30272a -page 55 pic16c71x t ab le 8-7: status bits and their significance , pic16c71 t ab le 8-8: status bits and their significance , pic16c710/711 t ab le 8-9: status bits and their significance , pic16c715 t o pd 1 1 p o w er-on reset 0 x illegal, t o is set on por x 0 illegal, pd is set on por 0 1 wdt reset 0 0 wdt w ak e-up u u mclr reset dur ing nor mal oper ation 1 0 mclr reset dur ing sleep or interr upt w ak e-up from sleep por bor t o pd 0 x 1 1 p o w er-on reset 0 x 0 x illegal, t o is set on por 0 x x 0 illegal, pd is set on por 1 0 x x bro wn-out reset 1 1 0 1 wdt reset 1 1 0 0 wdt w ak e-up 1 1 u u mclr reset dur ing nor mal oper ation 1 1 1 0 mclr reset dur ing sleep or interr upt w ak e-up from sleep per por bo r t o pd 1 0 x 1 1 p o w er-on re set x 0 x 0 x illegal, t o is set on por x 0 x x 0 illegal, pd is set on por 1 1 0 x x bro wn-out r eset 1 1 1 0 1 wdt reset 1 1 1 0 0 wdt w ak e- up 1 1 1 u u mclr reset dur ing nor mal oper ation 1 1 1 1 0 mclr reset dur ing sleep or interr upt w ak e-up from sleep 0 1 1 1 1 p ar ity error reset 0 0 x x x illegal, per is set on por 0 x 0 x x illegal, per is set on bor
pic16c71x ds30272a -page 56 1997 microchip technology inc. t ab le 8-10: reset condition f or s pecial register s, pic16c710/71/711 t ab le 8-11: reset condition f or s pecial register s, pic16c715 condition pr ogram counter st a tus register pcon register pic16c710/711 p o w er-on reset 000h 0001 1xxx ---- --0x mclr reset dur ing nor mal oper ation 000h 000u uuuu ---- --uu mclr reset dur ing sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt w ak e-up pc + 1 uuu0 0uuu ---- --uu bro wn-out reset (pic16c710/711) 000h 0001 1uuu ---- --u0 interr upt w ak e-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unkno wn, - = unimplemented bit read as '0' . note 1: when the w ak e-up is due to an interr upt and the gie bit is set, the pc is loaded with the interr upt v ector (0004h). condition pr ogram counter st a tu s register pcon register p o w er- on reset 000h 0001 1xxx u --- - 1 0x mclr reset dur ing nor mal oper ation 000h 000u uuuu u --- - u uu mclr reset dur ing sleep 000h 0001 0uuu u --- - u uu wdt reset 000h 0000 1uuu u --- - u uu wdt w ak e-up pc + 1 uuu0 0uuu u --- - u uu bro wn-out r eset 000h 0001 1uuu u --- - u u0 p ar ity error reset 000h uuu1 0uuu u--- -0uu interr upt w ak e-up from sleep pc + 1 (1) uuu1 0uuu u --- - u uu legend: u = unchanged, x = unkno wn, - = unimplemented bit r ead as '0' . note 1: when the w ak e-up is due to an interr upt and the gie bit is set , t he pc is loaded w ith th e i nterr upt v ector (0004h) .
1997 microchip technology inc. ds30272a -page 57 pic16c71x t ab le 8-12: initialization conditions for all register s , pic16c710/71/711 register p o wer -on reset, br o wn-out reset (5) mclr resets wdt reset w ake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) st a tus 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu por t a ---x 0000 ---u 0000 ---u uuuu por tb xxxx xxxx uuuu uuuu uuuu uuuu pcla th ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) adres xxxx xxxx uuuu uuuu uuuu uuuu adcon0 00-0 0000 00-0 0000 uu-u uuuu option 1111 1111 1111 1111 uuuu uuuu trisa ---1 1111 ---1 1111 ---u uuuu trisb 1111 1111 1111 1111 uuuu uuuu pcon (4) ---- --0u ---- --uu ---- --uu adcon1 ---- --00 ---- --00 ---- --uu legend: u = unchanged, x = unkno wn, - = unimplemented bit, read as '0', q = v alue depends on condition note 1: one or more bits in intcon will be aff ected (to cause w ak e-up). 2: when the w ak e-up is due to an interr upt and the gie bit is set, the pc is loaded with the interr upt v ector (0004h). 3: see t ab le 8-10 f or reset v alue f or speci c condition. 4: the pcon register is not implemented on the pic16c71. 5: bro wn-out reset is not implemented on the pic16c71.
pic16c71x ds30272a -page 58 1997 microchip technology inc. t ab le 8-13: initialization conditions f or all register s, pic16c715 register p o wer -on reset, br o wn-out reset p arity err or reset mclr resets wdt reset w ake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 pc + 1 (2) st a tus 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu por t a ---x 0000 ---u 0000 ---u uuuu por tb xxxx xxxx uuuu uuuu uuuu uuuu pcla th ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) pir1 -0-- ---- -0-- ---- -u-- ---- (1) adcon0 0000 00-0 0000 00-0 uuuu uu-u option 1111 1111 1111 1111 uuuu uuuu trisa ---1 1111 ---1 1111 ---u uuuu trisb 1111 1111 1111 1111 uuuu uuuu pie1 -0-- ---- -0-- ---- -u-- ---- pcon ---- -qqq ---- -1uu ---- -1uu adcon1 ---- --00 ---- --00 ---- --uu legend: u = unchanged, x = unkno wn, - = unimplemented bit, read as '0', q = v alue depends on condition note 1: one or more bits in intcon and pir1 will be aff ected (to cause w ak e-up). 2: when the w ak e-up is due to an interr upt and the gie bit is set, the pc is loaded with the interr upt v ector (0004h). 3: see t ab le 8-11 f or reset v alue f or speci c condition.
1997 microchip technology inc. ds30272a -page 59 pic16c71x figure 8-11: time-out sequence on p o wer -up ( mclr not tied to v dd ): case 1 figure 8-12: time-out sequence on p o wer -up ( mclr not tied t o v dd ): case 2 figure 8-13: time-out sequence on p o wer -up ( mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset
pic16c71x ds30272a -page 60 1997 microchip technology inc. figure 8-14: external p o wer -on reset cir cuit (f or slo w v dd p o wer -up) note 1: exter nal p o w er-on reset circuit is required only if v dd po w er-up slope is too slo w . the diode d helps discharge the capacitor quic kly when v dd po w ers do wn. 2: r < 40 k w is recommended to mak e sure that v oltage drop across r does not violate the de vice s electr ical speci cation. 3: r1 = 100 w to 1 k w will limit an y current o wing into mclr from e xter nal capacitor c in the e v ent of mclr/ v pp pin break- do wn due to electrostatic discharge (esd) or electr ical ov erstress (eos). c r1 r d v dd mclr pic16cxx figure 8-15: external br o wn-out pr otection cir cuit 1 figure 8-16: external br o wn-out pr otection cir cuit 2 note 1: this circuit will activ ate reset when v dd goes belo w (vz + 0.7v) where vz = zener v oltage . 2: inter nal bro wn-out detection on the pic16c710/711/715 s hould be disab led when using this circuit. 3: resistors should be adjusted f or the char- acter istics of the tr ansistor . v dd 33k 10k 40k v dd mclr pic1 6c xx note 1: this bro wn-out circuit is less e xpensiv e , albeit less accur ate . t r ansistor q1 tur ns off when v dd is belo w a cer tain le v el such that: 2: inter nal bro wn-out detection on the pic16c710/711/715 should be disab led when using this circuit. 3: resistors should be adjusted f or the char acter istics of the tr ansistor . v dd r1 r1 + r2 = 0.7v v dd r2 40k v dd mclr pic1 6c xx r1 q1
1997 microchip technology inc. ds30272a -page 61 pic16c71x 8.5 interrupts the pic16c71x f amily has 4 sources of interr upt . t he interr upt control register (intcon) records indi- vidual interr upt requests in ag bits . it also has individ- ual and global interr upt enab le bits . a global interr upt enab le bit, gie (intcon<7>) enab les (if set) all un-mask ed interr upts or disab les (if cleared) all interr upts . when bit gie is enab led, and an interr upt s ag bit and mask bit are set, the interr upt will v ector immediately . individual interr upts can be dis- ab led through their corresponding enab le bits in v ar i- ous registers . individual interr upt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ?etur n from interr upt instr uction, retfie , e xits the interr upt routine as w ell as sets the gie bit, which re-enab les interr upts . the rb0/int pin interr upt, the rb por t change inter- r upt and the tmr0 o v er o w interr upt ags are con- tained in the intcon register . the per ipher al interr upt ags are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interr upt enab le bits are contained in special function registers pie1 and pie2, and the per ipher al interr upt enab le bit is contained in special function reg- ister intcon. when an interr upt is responded to , the gie bit is cleared to disab le an y fur ther interr upt, the retur n address is pushed onto the stac k and the pc is loaded with 0004h. once in the interr upt ser vice routine the source(s) of the interr upt can be deter mined b y polling the interr upt ag bits . the interr upt ag bit(s) m ust be cleared in softw are bef ore re-enab ling interr upts to a v oid recursiv e interr upts . applicable devices 710 71 711 715 inte rrupt sour ces exter nal interr upt rb0/int tmr0 o v er o w interr upt por tb change interr upts (pins rb 7 : rb 4 ) a/d interr upt note: individual interr upt ag bits are set regard- less of the status of their corresponding mask bit or the gie bit. f or e xter nal interr upt e v ents , such as the int pin or por tb change interr upt, the interr upt latency will be three or f our instr uction cycles . the e xact latency depends when the interr upt e v ent occurs ( figure 8-19 ). the latency is the same f or one or tw o cycle instr uc- tions . individual interr upt ag bits are set regardless of the status of their corresponding mask bit or the gie bit. note: f or the pic16c71 if an interr upt occurs while the global inter- r upt enab le (gie) bit is being cleared, the gie bit ma y unintentionally be re-enab led b y the user s interr upt ser vice routine (the retfie instr uction). the e v ents that w ould cause this to occur are: 1. an instr uction clears the gie bit while an interr upt is ac kno wledged. 2. the prog r am br anches to the interr upt v ector and e x ecutes the interr upt ser- vice routine . 3. the interr upt ser vice routine com- pletes with the e x ecution of the ret- fie instr uction. this causes the gie bit to be set (enab les interr upts), and the prog r am retur ns to the instr uction after the one which w as meant to dis- ab le interr upts . p erf or m the f ollo wing to ensure that inter- r upts are globally disab led: loop bcf intcon, gie ; disable global ; interrupt bit btfsc intcon, gie ; global interrupt ; disabled? goto loop ; no, try again : ; yes, continue ; with program ; flow
pic16c71x ds30272a -page 62 1997 microchip technology inc. figure 8-17: interrupt logic, pic16c710, 71, 711 figure 8-18: i nterrupt logic , pic16c715 rbi f rbi e t0 if t0 ie intf inte gie adie w ak eup (if in sleep mode) interr upt to cpu adif rbi f rbi e t0 if t0 ie intf inte gie w ak eup (if in sleep mode) interr upt to cpu adif adif adie
1997 microchip technology inc. ds30272a -page 63 pic16c71x 8.5.1 int interr upt exter nal interr upt on rb0/int pin is edge tr iggered: either r ising if bit intedg (option<6>) is set, or f all- ing, if the intedg bit is clear . when a v alid edge appears on the rb0/int pin, ag bit intf (intcon<1>) is set. this interr upt can be disab led b y clear ing enab le bit inte (intcon<4>). flag bit intf m ust be cleared in softw are in the interr upt ser vice rou- tine bef ore re-enab ling this interr upt. the int interr upt can w ak e-up the processor from sleep , if bit inte w as set pr ior to going into sleep . the status of global inter- r upt enab le bit gie decides whether or not the proces- sor br anches to the interr upt v ector f ollo wing w ak e-up . see section 8.8 f or details on sleep mode . 8.5.2 tmr0 interr upt an o v er o w (ffh ? 00h) in the tmr0 register will set ag bit t0if (intcon<2>). the interr upt can be enab led/disab led b y setting/clear ing enab le bit t0ie (intcon<5>). ( section 6.0 ) 8.5.3 p or tb intcon change an input change on por tb<7:4> sets ag bit rbif (intcon<0>). the interr upt can be enab led/disab led b y setting/clear ing enab le bit rbie (intcon<4>). ( section 5.2 ) note: f or the pic16c71 if a change on the i/o pin should occur when the read oper ation is being e x ecuted (star t of the q2 cycle), then the rbif inter- r upt ag ma y not get set. figure 8-19: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clk out int pin intf ag (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instr uction f etched instr uction e x ecuted interr upt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dumm y cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dumm y cycle inst (pc) 1 4 5 1 note 1: intf ag is sampled here (e v er y q1). 2: interr upt latency = 3-4 tcy where tcy = instr uction cycle time . latency is the same whether inst (pc) is a single cycle or a 2-cycle instr uction. 3: clk out is a v ailab le only in rc oscillator mode . 4: f or minim um width of int pulse , ref er to a c specs . 5: intf is enab led to be set an ytime dur ing the q4-q1 cycles . 2 3
pic16c71x ds30272a -page 64 1997 microchip technology inc. 8.6 conte xt sa ving during interrupts dur ing an interr upt, only the retur n pc v alue is sa v ed on the stac k. t ypically , users ma y wish to sa v e k e y reg- isters dur ing an interr upt i.e ., w register and st a tus register . this will ha v e to be implemented in softw are . example 8-1 stores and restores the st a tus and w registers . the user register , st a tus_temp , m ust be de ned in bank 0. the e xample: a) stores the w register . b) stores the st a tus register in bank 0. c) ex ecutes the isr code . d) restores the st a tus register (and bank select bit). e) restores the w register . example 8-1: sa ving st a tus and w register s in ram movwf w_temp ; copy w to temp register, could be bank one or zero swapf status,w ; swap status to be saved into w movwf status_temp ; save status to bank zero status_temp register : :(isr) : swapf status_temp,w ; swap status_temp register into w ;(sets bank to original state) movwf status ; move w into status register swapf w_temp,f ; swap w_temp swapf w_temp,w ; swap w_temp into w
1997 microchip technology inc. ds30272a -page 65 pic16c71x 8.7 w atc hdog timer (wdt) the w atchdog timer is as a free r unning on-chip rc oscillator which does not require an y e xter nal compo- nents . this rc oscillator is separ ate from the rc oscil- lator of the osc1/clkin pin. that means that the wdt will r un, e v en if the cloc k on the osc1/clkin and osc2/clk out pins of the de vice has been stopped, f or e xample , b y e x ecution of a sleep instr uction. dur- ing nor mal oper ation, a wdt time-out gener ates a de vice reset (w atchdog timer reset). if the de vice is in sleep mode , a wdt time-out causes the de vice to w ak e-up and contin ue with nor mal oper ation (w atch- dog timer w ak e-up). the wdt can be per manently disab led b y clear ing con gur ation bit wdte ( section 8.1 ). 8.7.1 wdt p er iod the wdt has a nominal time-out per iod of 18 ms , (with no prescaler). the time-out per iods v ar y with temper a- ture , v dd and process v ar iations from par t to par t (see dc specs). if longer time-out per iods are desired, a prescaler with a division r atio of up to 1:128 can be applicable devices 710 71 711 715 assigned to the wdt under softw are control b y wr iting to the option register . thus , time-out per iods up to 2.3 seconds can be realiz ed. the clrwdt and sleep instr uctions clear the wdt and the postscaler , if assigned to the wdt , and pre v ent it from timing out and gener ating a de vice reset condi- tion. the t o bit in the st a tus register will be cleared upon a w atchdog timer time-out. 8.7.2 wdt prog r amming consider ations it should also be tak en into account that under w orst case conditions ( v dd = min., t emper ature = max., and max. wdt prescaler) it ma y tak e se v er al seconds bef ore a wdt time-out occurs . note: when a clrwdt instr uction is e x ecuted and the prescaler is assigned to the wdt , the prescaler count will be cleared, b ut the prescaler assignment is not changed. figure 8-20: w atc hdog timer bloc k dia gram figure 8-21: summar y of w atc hdog timer register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con g. bits (1) boden (1) cp1 cp0 pwr te (1) wdte fosc1 fosc0 81h ,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used b y the w atchdog timer . note 1: see figure 8-1 , figure 8-2 and figure 8-3 f or oper ation of these bits . f rom tmr0 cloc k source ( figure 6-6 ) t o tmr0 ( figure 6-6 ) p ostscaler wdt timer wdt enab le bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register . 8
pic16c71x ds30272a -page 66 1997 microchip technology inc. 8.8 p o wer -do wn mode (sleep) p o w er-do wn mode is entered b y e x ecuting a sleep instr uction. if enab led, the w atchdog timer will be cleared b ut k eeps r unning, the pd bit (st a tus<3>) is cleared, the t o (st a tus<4>) bit is set, and the oscillator dr iv er is tur ned off . the i/o por ts maintain the status the y had, bef ore the sleep instr uction w as e x ecuted (dr iving high, lo w , or hi-impedance). f or lo w est current consumption in this mode , place all i/o pins at either v dd , or v ss , ensure no e xter nal cir- cuitr y is dr a wing current from the i/o pin, po w er-do wn the a/d , disab le e xter nal cloc ks . pull all i/o pins , that are hi-impedance inputs , high or lo w e xter nally to a v oid s witching currents caused b y oating inputs . the t0cki input should also be at v dd or v ss f or lo w est current consumption. the contr ib ution from on-chip pull-ups on por tb should be considered. the mclr pin m ust be at a logic high le v el ( v ihmc ). 8.8.1 w ak e-up from sleep the de vice can w ak e up from sleep through one of the f ollo wing e v ents: 1. exter nal reset input on mclr pin. 2. w atchdog timer w ak e-up (if wdt w as enab led). 3. interr upt from int pin, rb por t change , or some p er ipher al interr upts . exter nal mclr reset will cause a de vice reset. all other e v ents are considered a contin uation of prog r am e x ecution and cause a "w ak e-up". the t o and pd bits in the st a tus register can be used to deter mine the cause of de vice reset. the pd bit, which is set on po w er-up , is cleared when sleep is in v ok ed. the t o bit is cleared if a wdt time-out occurred (and caused w ak e-up). the f ollo wing per ipher al interr upts can w ak e the de vice from sleep: 1. tmr1 interr upt. timer1 m ust be oper ating as an asynchronous counter . 2. a/d con v ersion (when a/d cloc k source is rc). other per ipher als cannot gener ate interr upts since dur- ing sleep , no on-chip q cloc ks are present. when the sleep instr uction is being e x ecuted, the ne xt instr uction (pc + 1) is pre-f etched. f or the de vice to w ak e-up through an interr upt e v ent, the corresponding interr upt enab le bit m ust be set (enab led). w ak e-up is regardless of the state of the gie bit. if the gie bit is clear (disab led), the de vice contin ues e x ecution at the instr uction after the sleep instr uction. if the gie bit is set (enab led), the de vice e x ecutes the instr uction after the sleep instr uction and then br anches to the inter- r upt address (0004h). in cases where the e x ecution of the instr uction f ollo wing sleep is not desir ab le , the user should ha v e a nop after the sleep instr uction. 8.8.2 w ak e-up using interr upts when global interr upts are disab led (gie cleared) and an y interr upt source has both its interr upt enab le bit and interr upt ag bit set, one of the f ollo wing will occur : if the interr upt occurs bef ore the the e x ecution of a sleep instr uction, the sleep instr uction will complete as a nop . theref ore , the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bits will not be cleared. if the interr upt occurs during or after the e x ecu- tion of a sleep instr uction, the de vice will immedi- ately w ak e up from sleep . the sleep instr uction will be completely e x ecuted bef ore the w ak e-up . theref ore , the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. ev en if the ag bits w ere chec k ed bef ore e x ecuting a sleep instr uction, it ma y be possib le f or f lag bits to become set bef ore the sleep instr uction completes . t o deter mine whether a sleep instr uction e x ecuted, test the pd bit. if the pd bit is set, the sleep instr uction w as e x ecuted as a nop . t o ensure that the wdt is cleared, a clrwdt instr uc- tion should be e x ecuted bef ore a sleep instr uction.
1997 microchip technology inc. ds30272a -page 67 pic16c71x figure 8-22: w ake-up fr om sleep t hr ough interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clk out(4) int pin intf ag (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instr uction f etched instr uction e x ecuted pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interr upt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dumm y cycle pc + 2 0004h 0005h dumm y cycle t ost (2) pc+2 note 1: xt , hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (dr a wing not to scale) this dela y will not be there f or rc osc mode . 3: gie = '1' assumed. in this case after w ak e- up , the processor jumps to the interr upt routine . if gie = '0', e x ecution will contin ue in-line . 4: clk out is not a v ailab le in these osc modes , b ut sho wn here f or timing ref erence . 8.9 pr ogram v eri cation/code pr otection if the code protection bit(s) ha v e not been pro- g r ammed, the on-chip prog r am memor y can be read out f or v er i cation pur poses . 8.10 id locations f our memor y locations (2000h - 2003h) are designated as id locations where the user can store chec ksum or other code-identi cation n umbers . these locations are not accessib le dur ing nor mal e x ecution b ut are read- ab le and wr itab le dur ing prog r am/v er ify . it is recom- mended that only the 4 least signi cant bits of the id location are used. 8.11 in-cir cuit serial pr ogramming pic16cxx microcontrollers can be ser ially pro- g r ammed while in the end application circuit. this is simply done with tw o lines f or cloc k and data, and three other lines f or po w er , g round, and the prog r amming v oltage . this allo ws customers to man uf acture boards with unprog r ammed de vices , and then prog r am the microcontroller just bef ore shipping the product. this also allo ws the most recent r mw are or a custom r m- w are to be prog r ammed. note: microchip does not recommend code pro- tecting windo w ed de vices . the de vice is placed into a prog r am/v er ify mode b y holding the rb6 and rb7 pins lo w while r aising the mclr ( v pp ) pin from v il to v ihh ( see prog r amming speci cation). rb6 becomes the prog r amming cloc k and rb7 becomes the prog r amming data. both rb6 and rb7 are schmitt t r igger inputs in this mode . after reset, to place the de vice into prog r amming/v er ify mode , the prog r am counter (pc) is at location 00h. a 6- bit command is then supplied to the de vice . depending on the command, 14-bits of prog r am data are then sup- plied to or from the de vice , depending if the command w as a load or a read. f or complete details of ser ial pro- g r amming, please ref er to the pic16c6x/7x prog r am- ming speci cations (liter ature #ds30228). figure 8-23: t ypical in-cir cuit serial pr ogramming connection exter nal connector signals t o nor mal connections t o nor mal connections pic16cxx v dd v ss mclr / v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
pic16c71x ds30272a -page 68 1997 microchip technology inc. no tes:
1997 microchip technology inc. ds30272a -page 69 pic16c71x 9.0 instruction set summar y each pic16cxx instr uction is a 14-bit w ord divided into an opcode which speci es the instr uction type and one or more oper ands which fur ther specify the oper ation of the instr uction. the pic16cxx instr uction set summar y in t ab le 9-2 lists b yte-oriented , bit-ori- ented , and literal and contr ol oper ations . t ab le 9-1 sho ws the opcode eld descr iptions . f or b yte-oriented instr uctions , 'f' represents a le reg- ister designator and 'd' represents a destination desig- nator . the le register designator speci es which le register is to be used b y the instr uction. the destination designator speci es where the result of the oper ation is to be placed. if 'd' is z ero , the result is placed in the w register . if 'd' is one , the result is placed in the le register speci ed in the instr uction. f or bit-oriented instr uctions , 'b' represents a bit eld designator which selects the n umber of the bit aff ected b y the oper ation, while 'f' represents the n umber of the le in which the bit is located. f or literal and contr ol oper ations , 'k' represents an eight or ele v en bit constant or liter al v alue . t ab le 9-1: op code field descriptions the instr uction set is highly or thogonal and is g rouped into three basic categor ies: field description f register le address (0x00 to 0x7f) w w or king register (accum ulator) b bit address within an 8-bit le register k liter al eld, constant data or label x don't care location (= 0 or 1) the assemb ler will gener ate code with x = 0. it is the recommended f or m of use f or compatibility with all microchip softw are tools . d destination select; d = 0: store result in w , d = 1: store result in le register f . def ault is d = 1 label label name tos t op of stac k pc prog r am counter pclath prog r am counter high latch gie global interr upt enab le bit wdt w atchdog timer/counter to time-out bit pd p o w er-do wn bit dest destination either the w register or the speci ed register le location [ ] options ( ) contents ? assigned to < > register bit eld ? in the set of i talics user de ned ter m (f ont is cour ier) byte-oriented oper ations bit-oriented oper ations literal and contr ol oper ations all instr uctions are e x ecuted within one single instr uc- tion cycle , unless a conditional test is tr ue or the pro- g r am counter is changed as a result of an instr uction. in this case , the e x ecution tak es tw o instr uction cycles with the second cycle e x ecuted as a nop . one instr uc- tion cycle consists of f our oscillator per iods . thus , f or an oscillator frequency of 4 mhz, the nor mal instr uction e x ecution time is 1 m s . if a conditional test is tr ue or the prog r am counter is changed as a result of an instr uc- tion, the instr uction e x ecution time is 2 m s . t ab le 9-2 lists the instr uctions recogniz ed b y the mp asm assemb ler . figure 9-1 sho ws the g ener al f or mats that the instr uc- tions can ha v e . all e xamples use the f ollo wing f or mat to represent a he xadecimal n umber : 0xhh where h signi es a he xadecimal digit. figure 9-1: general fo rmat f or instructions note: t o maintain upw ard compatibility with future pic16cxx products , do not use the option and tris instr uctions . byte-oriented le register oper ations 13 8 7 6 0 d = 0 f or destination w opcode d f (file #) d = 1 f or destination f f = 7-bit le register address bit-oriented le register oper ations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit le register address literal and contr ol oper ations 13 8 7 0 opcode k ( liter al) k = 8-bit immediate v alue 13 11 10 0 opcode k ( liter al) k = 11-bit immediate v alue gener al call and goto instr uctions only
pic16c71x ds30272a -page 70 1997 microchip technology inc. t ab le 9-2: pic16cxx instruction set mnemonic, operands description cyc les 14-bit opcode status aff ected notes msb lsb byte-oriented file register opera tions add wf and wf clrf clr w comf decf decfsz incf incfsz ior wf mo vf mo vwf nop rlf rrf subwf sw apf xor wf f , d f , d f - f , d f , d f , d f , d f , d f , d f , d f - f , d f , d f , d f , d f , d add w and f and w with f clear f clear w complement f decrement f decrement f , skip if 0 increment f increment f , skip if 0 inclusiv e or w with f mo v e f mo v e w to f no oper ation rotate left f through carr y rotate right f through carr y subtr act w from f sw ap nib b les in f exclusiv e or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c ,dc ,z z z z z z z z z c c c ,dc ,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit -oriented file register opera tions bcf bsf btfsc btfss f , b f , b f , b f , b bit clear f bit set f bit t est f , skip if clear bit t est f , skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and contr ol opera tions addl w andl w call clr wdt go t o iorl w mo vl w retfie retl w return sleep subl w xorl w k k k - k k k - k - - k k add liter al and w and liter al with w call subroutine clear w atchdog timer go to address inclusiv e or liter al with w mo v e liter al to w retur n from interr upt retur n with liter al in w retur n from subroutine go into standb y mode subtr act w from liter al exclusiv e or liter al with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c ,dc ,z z t o , pd z t o , pd c ,dc ,z z note 1: when an i/o register is modi ed as a function of itself ( e .g., movf portb, 1 ), the v alue used will be that v alue present on the pins themselv es . f or e xample , if the data latch is '1' f or a pin con gured as input and is dr iv en lo w b y an e xter nal de vice , the data will be wr itten bac k with a '0'. 2: if this instr uction is e x ecuted on the tmr0 register (and, where applicab le , d = 1), the prescaler will be cleared if assigned to the timer0 module . 3: if prog r am counter (pc) is modi ed or a conditional test is tr ue , the instr uction requires tw o cycles . the second cycle is e x ecuted as a nop .
1997 microchip technology inc. ds30272a -page 71 pic16c71x 9.1 instruction descriptions addl w ad d literal and w syntax: [ label ] addl w k oper ands: 0 k 255 oper ation: (w) + k ? (w) status aff ected: c , dc , z encoding: 11 111x kkkk kkkk descr iption: the contents of the w register are added to the eight bit liter al 'k' and the result is placed in the w register . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read liter al 'k' process data wr ite to w example: addlw 0x15 bef ore instr uction w = 0x10 after instr uction w = 0x25 add wf ad d w and f syntax: [ label ] add wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) + (f) ? (dest) status aff ected: c , dc , z encoding: 00 0111 dfff ffff descr iption: add the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example addwf fsr, 0 bef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0xd9 fsr = 0xc2 andl w and literal with w syntax: [ label ] andl w k oper ands: 0 k 255 oper ation: (w) .and . (k) ? (w) status aff ected: z encoding: 11 1001 kkkk kkkk descr iption: the contents of w register are and?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read liter al "k" process data wr ite to w example andlw 0x5f bef ore instr uction w = 0xa3 after instr uction w = 0x03 and wf and w with f syntax: [ label ] and wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .and . (f) ? (dest) status aff ected: z encoding: 00 0101 dfff ffff descr iption: and the w register with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example andwf fsr, 1 bef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0x17 fsr = 0x02
pic16c71x ds30272a -page 72 1997 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f ,b oper ands: 0 f 127 0 b 7 oper ation: 0 ? (f) status aff ected: none encoding: 01 00bb bfff ffff descr iption: bit 'b' in register 'f' is cleared . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite register 'f' example bcf flag_reg, 7 bef ore instr uction fla g_reg = 0xc7 after instr uction fla g_reg = 0x47 bsf bit set f syntax: [ label ] bsf f ,b oper ands: 0 f 127 0 b 7 oper ation: 1 ? (f) status aff ected: none encoding: 01 01bb bfff ffff descr iption: bit 'b' in register 'f' is set. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite register 'f' example bsf flag_reg, 7 bef ore instr uction fla g_reg = 0x0a after instr uction fla g_reg = 0x8a btfsc bit t est, skip if clear syntax: [ label ] btfsc f ,b oper ands: 0 f 127 0 b 7 oper ation: skip if (f) = 0 status aff ected: none encoding: 01 10bb bfff ffff descr iption: if bit 'b' in register 'f' is ' 1' then the ne xt instr uction is e x ecuted. if bit 'b' , in register 'f', i s '0' then the ne xt instr uction i s discarded, and a nop is e x ecuted instead, making this a 2 t cy i nstr uction . w ords: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data nop if skip : (2nd cycle) q1 q2 q3 q4 nop nop nop nop example here false true btfsc goto flag,1 process_code bef ore instr uction pc = address here after instr uction if fla g<1> = 0, pc = address true if fla g<1>=1, pc = address false
1997 microchip technology inc. ds30272a -page 73 pic16c71x btfss bit t est f , skip if set syntax: [ label ] btfss f ,b oper ands: 0 f 127 0 b < 7 oper ation: skip if (f) = 1 status aff ected: none encoding: 01 11bb bfff ffff descr iption: if bit 'b' in register 'f' is ' 0' then the ne xt instr uction is e x ecuted. if bit 'b' is '1', then the ne xt instr uction i s discarded and a nop is e x ecuted instead, making this a 2 t cy i nstr uction. w ords: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data nop if skip : (2nd cycle) q1 q2 q3 q4 nop nop nop nop example here false true btfsc goto flag,1 process_code bef ore instr uction pc = address here after instr uction if fla g<1> = 0, pc = address false if fla g<1> = 1, pc = address true call call subr outine syntax: [ label ] call k oper ands: 0 k 2047 oper ation: (pc)+ 1 ? t os , k ? pc<10:0>, (pcla th<4:3>) ? pc<12:11> status aff ected: none encoding: 10 0kkk kkkk kkkk descr iption: call subroutine . first, retur n address (pc+1) is pushed onto the stac k. the ele v en bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pcla th. call is a tw o cycle instr uction. w ords: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read liter al 'k', push pc to stac k process data wr ite to pc 2nd cycle nop nop nop nop example here call there bef ore instr uction pc = address here after instr uction pc = address there t os = address here+1
pic16c71x ds30272a -page 74 1997 microchip technology inc. clrf clear f syntax: [ label ] clrf f oper ands: 0 f 127 oper ation: 00h ? (f) 1 ? z status aff ected: z encoding: 00 0001 1fff ffff descr iption: the contents of register 'f' are cleared and the z bit is set. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite register 'f' example clrf flag_reg bef ore instr uction fla g_reg = 0x5a after instr uction fla g_reg = 0x00 z = 1 clr w clear w syntax: [ label ] clr w oper ands: none oper ation: 00h ? (w) 1 ? z status aff ected: z encoding: 00 0001 0xxx xxxx descr iption: w register is cleared. zero bit (z) is set. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode nop process data wr ite to w example clrw bef ore instr uction w = 0x5a after instr uction w = 0x00 z = 1 clr wdt clear w atc hdog timer syntax: [ label ] clr wdt oper ands: none oper ation: 00h ? wdt 0 ? wdt prescaler , 1 ? t o 1 ? pd status aff ected: t o , pd encoding: 00 0000 0110 0100 descr iption: clrwdt instr uction resets the w atch- dog timer . it also resets the prescaler of the wdt . status bits t o and pd are set. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode nop process data clear w dt co unter example clrwdt bef ore instr uction wdt counter = ? after instr uction wdt counter = 0x00 wdt prescaler = 0 t o = 1 pd = 1
1997 microchip technology inc. ds30272a -page 75 pic16c71x comf complement f syntax: [ label ] comf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: ( f ) ? (dest) status aff ected: z encoding: 00 1001 dfff ffff descr iption: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in w . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr it e to dest example comf reg1,0 bef ore instr uction reg1 = 0x13 after instr uction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) - 1 ? (dest) status aff ected: z encoding: 00 0011 dfff ffff descr iption: decrement register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example decf cnt, 1 bef ore instr uction cnt = 0x01 z = 0 after instr uction cnt = 0x00 z = 1 decfsz decrement f , skip if 0 syntax: [ label ] decfsz f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) - 1 ? (dest); skip if result = 0 status aff ected: none encoding: 00 1011 dfff ffff descr iption: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 1, the ne xt instr uction, i s e x ecuted. if the result is 0, then a n op is e x ecuted instead making it a 2t cy i nstr uction. w ords: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest if skip : (2nd cycle) q1 q2 q3 q4 nop nop nop nop example here decfsz cnt, 1 goto loop continue bef ore instr uction pc = address here after instr uction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt 1 0, pc = address here+1
pic16c71x ds30272a -page 76 1997 microchip technology inc. go t o unconditional branc h syntax: [ label ] go t o k oper ands: 0 k 2047 oper ation: k ? pc<10:0> pcla th<4:3> ? pc<12:11> status aff ected: none encoding: 10 1kkk kkkk kkkk descr iption: goto is an unconditional br anch. the ele v en bit immediate v alue is loaded into pc bits <10:0>. the upper bits of pc are loaded from pcla th<4:3>. goto is a tw o cycle instr uction. w ords: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read liter al 'k' process data wr ite to pc 2nd cycle nop nop nop nop example goto there after instr uction pc = address there incf increment f syntax: [ label ] incf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) + 1 ? (dest) status aff ected: z encoding: 00 1010 dfff ffff descr iption: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example incf cnt, 1 bef ore instr uction cnt = 0xff z = 0 after instr uction cnt = 0x00 z = 1
1997 microchip technology inc. ds30272a -page 77 pic16c71x incfsz increment f , skip if 0 syntax: [ label ] incfsz f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) + 1 ? (dest), skip if result = 0 status aff ected: none encoding: 00 1111 dfff ffff descr iption: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 1, the ne xt instr uction i s e x ecuted. if the result is 0, a n op is e x ecuted instead making it a 2t cy i nstr uction . w ords: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest if skip : (2nd cycle) q1 q2 q3 q4 nop nop nop nop example here incfsz cnt, 1 goto loop continue bef ore instr uction pc = address here after instr uction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 1 0, pc = address here +1 iorl w inc lusive or literal with w syntax: [ label ] iorl w k oper ands: 0 k 255 oper ation: (w) .or. k ? (w) status aff ected: z encoding: 11 1000 kkkk kkkk descr iption: the contents of the w register is or?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read liter al 'k' process data wr ite to w example iorlw 0x35 bef ore instr uction w = 0x9a after instr uction w = 0xbf z = 1
pic16c71x ds30272a -page 78 1997 microchip technology inc. ior wf inc lusive or w with f syntax: [ label ] ior wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .or. (f) ? (dest) status aff ected: z encoding: 00 0100 dfff ffff descr iption: inclusiv e or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example iorwf result, 0 bef ore instr uction resul t = 0x13 w = 0x91 after instr uction resul t = 0x13 w = 0x93 z = 1 mo vf mo ve f syntax: [ label ] mo vf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) ? (dest) status aff ected: z encoding: 00 1000 dfff ffff descr iption: the contents of register f is mo v ed to a destination dependant upon the sta- tus of d. if d = 0, destination is w reg- ister . if d = 1, the destination is le register f itself . d = 1 is useful to test a le register since status ag z is aff ected. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example movf fsr, 0 after instr uction w = v alue in fsr register z = 1 mo vl w mo ve literal to w syntax: [ label ] mo vl w k oper ands: 0 k 255 oper ation: k ? (w) status aff ected: none encoding: 11 00xx kkkk kkkk descr iption: the eight bit liter al 'k' is loaded into w register . the don? cares will assemb le as 0 s . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read liter al 'k' process data wr ite to w example movlw 0x5a after instr uction w = 0x5a mo vwf mo ve w to f syntax: [ label ] mo vwf f oper ands: 0 f 127 oper ation: (w) ? (f) status aff ected: none encoding: 00 0000 1fff ffff descr iption: mo v e data from w register to register 'f' . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite register 'f' example movwf option _reg bef ore instr uction option = 0xff w = 0x4f after instr uction option = 0x4f w = 0x4f
1997 microchip technology inc. ds30272a -page 79 pic16c71x nop no operation syntax: [ label ] nop oper ands: none oper ation: no oper ation status aff ected: none encoding: 00 0000 0xx0 0000 descr iption: no oper ation. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode nop nop nop example nop option load option register syntax: [ label ] option oper ands: none oper ation: (w) ? option status aff ected: none encoding: 00 0000 0110 0010 descr iption: the contents of the w register are loaded in the option register . this instr uction is suppor ted f or code com- patibility with pic16c5x products . since option is a readab le/wr itab le register , the user can directly address it. w ords: 1 cycles: 1 example t o maintain upwar d compatibility with future pic16cxx pr oducts, do not use this instruction. retfie return fr om interrupt syntax: [ label ] retfie oper ands: none oper ation: t os ? pc , 1 ? gie status aff ected: none encoding: 00 0000 0000 1001 descr iption: retur n from interr upt. stac k is pop ed and t op of stac k (t os) is loaded in the pc . interr upts are enab led b y set- ting global interr upt enab le bit, gie (intcon<7>). this is a tw o cycle instr uction. w ords: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode nop set the gie bit p op from the stac k 2nd cycle nop nop nop nop example retfie after interr upt pc = t os gie = 1
pic16c71x ds30272a -page 80 1997 microchip technology inc. retl w return with literal in w syntax: [ label ] retl w k oper ands: 0 k 255 oper ation: k ? (w); t os ? pc status aff ected: none encoding: 11 01xx kkkk kkkk descr iption: the w register is loaded with the eight bit liter al 'k'. the prog r am counter is loaded from the top of the stac k (the retur n address). this is a tw o cycle instr uction. w ords: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read liter al 'k' nop wr ite to w , p op from the stac k 2nd cycle nop nop nop nop example table call table ;w contains table ;offset value ; w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table bef ore instr uction w = 0x07 after instr uction w = v alue of k8 return return fr om subr outine syntax: [ label ] return oper ands: none oper ation: t os ? pc status aff ected: none encoding: 00 0000 0000 1000 descr iption: retur n from subroutine . the stac k is pop ed and the top of the stac k (t os) is loaded into the prog r am counter . this is a tw o cycle instr uction. w ords: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode nop nop p op from the stac k 2nd cycle nop nop nop nop example return after interr upt pc = t os
1997 microchip technology inc. ds30272a -page 81 pic16c71x rlf rotate left f thr ough carr y syntax: [ label ] rlf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: see descr iption belo w status aff ected: c encoding: 00 1101 dfff ffff descr iption: the contents of register 'f' are rotated one bit to the left through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example rlf reg1,0 bef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 1100 1100 c = 1 register f c rrf rotate right f thr ough carr y syntax: [ label ] rrf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: see descr iption belo w status aff ected: c encoding: 00 1100 dfff ffff descr iption: the contents of register 'f' are rotated one bit to the r ight through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example rrf reg1,0 bef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 0111 0011 c = 0 register f c
pic16c71x ds30272a -page 82 1997 microchip technology inc. sleep syntax: [ label ] sleep oper ands: none oper ation: 00h ? wdt , 0 ? wdt prescaler , 1 ? t o , 0 ? pd status aff ected: t o , pd encoding: 00 0000 0110 0011 descr iption: the po w er-do wn status bit, pd is cleared. time-out status bit, t o is set. w atchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 8.8 f or more details . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode nop nop go to sleep example: sleep subl w subtract w fr om literal syntax: [ label ] subl w k oper ands: 0 k 255 oper ation: k - (w) ? ( w) status aff ected: c , dc , z encoding: 11 110x kkkk kkkk descr iption: the w register is subtr acted (2 s comple- ment method) from the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read liter al 'k' process data wr ite to w example 1: sublw 0x02 bef ore instr uction w = 1 c = ? z = ? after instr uction w = 1 c = 1; result is positiv e z = 0 example 2: bef ore instr uction w = 2 c = ? z = ? after instr uction w = 0 c = 1; result is z ero z = 1 example 3: bef ore instr uction w = 3 c = ? z = ? after instr uction w = 0xff c = 0; result is nega- tiv e z = 0
1997 microchip technology inc. ds30272a -page 83 pic16c71x subwf subtract w fr om f syntax: [ label ] subwf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) - (w) ? ( dest) status aff ected: c , dc , z encoding: 00 0010 dfff ffff descr iption: subtr act (2 s complement method) w reg- ister from register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example 1: subwf reg1, 1 bef ore instr uction reg1 = 3 w = 2 c = ? z = ? after instr uction reg1 = 1 w = 2 c = 1; result is positiv e z = 0 example 2: bef ore instr uction reg1 = 2 w = 2 c = ? z = ? after instr uction reg1 = 0 w = 2 c = 1; result is z ero z = 1 example 3: bef ore instr uction reg1 = 1 w = 2 c = ? z = ? after instr uction reg1 = 0xff w = 2 c = 0; result is negativ e z = 0 sw apf swap nibb les in f syntax: [ label ] sw apf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f<3:0>) ? (dest<7:4>), (f<7:4>) ? (dest<3:0>) status aff ected: none encoding: 00 1110 dfff ffff descr iption: the upper and lo w er nib b les of regis- ter 'f' are e xchanged. if 'd' is 0 the result is placed in w register . if 'd' is 1 the result is placed in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example swapf reg, 0 bef ore instr uction reg1 = 0xa5 after instr uction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f oper ands: 5 f 7 oper ation: (w) ? tris register f; status aff ected: none encoding: 00 0000 0110 0fff descr iption: the instr uction is suppor ted f or code compatibility with the pic16c5x prod- ucts . since tris registers are read- ab le and wr itab le , the user can directly address them. w ords: 1 cycles: 1 example t o maintain upwar d compatibility with future pic16cxx pr oducts, do not use this instruction.
pic16c71x ds30272a -page 84 1997 microchip technology inc. xorl w exc lusive or literal with w syntax: [ label ] xorl w k oper ands: 0 k 255 oper ation: (w) .xor. k ? ( w) status aff ected: z encoding: 11 1010 kkkk kkkk descr iption: the contents of the w register are xor?d with the eight bit liter al 'k'. the result is placed in the w regis- ter . w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read liter al 'k' process data wr ite to w example: xorlw 0xaf bef ore instr uction w = 0xb5 after instr uction w = 0x1a xor wf exc lusive or w with f syntax: [ label ] xor wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .xor. (f) ? ( dest) status aff ected: z encoding: 00 0110 dfff ffff descr iption: exclusiv e or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data wr ite to dest example xorwf reg 1 bef ore instr uction reg = 0xaf w = 0xb5 after instr uction reg = 0x1a w = 0xb5
pic16c71x 1997 microchip technology inc. ds30272a -page 85 10.0 de velopment suppor t 10.1 de velopme nt t ools the pic micr o? microcontrollers are suppor ted with a full r ange of hardw are and softw are de v elopment tools: picmaster/picmaster ce real-time in-circuit em ulator icepic lo w-cost pic16c5x and pic16cxxx in-circuit em ulator pr o ma te a ii univ ersal prog r ammer picst ar t a plus entr y-le v el prototype prog r ammer picdem-1 lo w-cost demonstr ation board picdem-2 lo w-cost demonstr ation board picdem-3 lo w-cost demonstr ation board mp asm assemb ler mplab ? sim softw are sim ulator mplab-c (c compiler) fuzzy logic de v elopment system ( fuzzy tech a - mp) 10.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster univ ersal in-circuit em ulator is intended to pro vide the product de v elopment engineer with a complete microcontroller design tool set f or all microcontrollers in the pic12c x xx, pic14c000, pic16c5x, pic16cxxx and pic17cxx f amilies . picmaster is supplied with the mplab ? integ r ated de v elopment en vironment (ide), which allo ws editing, ?ak e and do wnload, and source deb ugging from a single en vironment . i nterchangeab le target probes allo w the system to be easily recon gured f or em ulation of diff erent proces- sors . the univ ersal architecture of the picmaster allo ws e xpansion to suppor t all ne w microchip micro- controllers . the picmaster em ulator system has been designed as a real-time em ulation system with adv anced f eatures that are gener ally f ound on more e xpensiv e de v elopment tools . the pc compatib le 386 (and higher) machine platf or m and microsoft win do ws a 3.x en vironment w ere chosen to best mak e these f ea- tures a v ailab le to y ou, the end user . a ce compliant v ersion of picmaster is a v ailab le f or european union (eu) countr ies . 10.3 icepic: lo w-cost pic16cxxx in-cir cuit em ulator icepic is a lo w-cost in-circuit em ulator solution f or the microchip pic16c5x and pic16cxxx f amilies of 8-bit o tp microcontrollers . icepic is designed to oper ate on pc-compatib le machines r anging from 286-a t a through p entium ? based machines under windo ws 3.x en vironment. icepic f eatures real time , non-intr usiv e em ulation. 10.4 pr o ma te ii: univer sal pr ogrammer the pr o ma te ii univ ersal prog r ammer is a full-f ea- tured prog r ammer capab le of oper ating in stand-alone mode as w ell as pc-hosted mode . the pr o ma te ii has prog r ammab le v dd and v pp supplies which allo ws it to v er ify prog r ammed memor y at v dd min and v dd max f or maxim um reliability . it has an lcd displa y f or displa ying error messages , k e ys to enter commands and a modular detachab le soc k et assemb ly to suppor t v ar ious pac kage types . in stand- alone mode the pr o ma te ii can read, v er ify or pro- g r am pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices . it can also set con gur ation and code-protect bits in this mode . 10.5 p icst ar t plus entr y le vel de velopment system the picst ar t prog r ammer is an easy-to-use , lo w- cost prototype prog r ammer . it connects to the pc via one of the com (rs-232) por ts . mplab integ r ated de v elopment en vironment softw are mak es using the prog r ammer simple and ef cient. picst ar t plus is not recommended f or production prog r amming. picst ar t plus suppor ts all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices with up to 40 pins . larger pin count de vices such as the pic16c923 and pic16c924 ma y be suppor ted with an adapter soc k et.
pic16c71x ds30272a -page 86 1997 microchip technology inc. 10.6 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstr ates the capabilities of se v er al of microchip s microcontrol- lers . the microcontrollers suppor ted are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessar y hardw are and softw are is included to r un basic demo prog r ams . the users can prog r am the sample micro controllers pro vided with the picdem-1 board, on a pr o ma te ii or picst ar t -plus prog r ammer , and easily test r m- w are . the user can also connect the picdem-1 board to the picmaster em ulator and do wn load the r mw are to the em ulator f or testing. additional pro- totype area is a v ailab le f or the user to b uild some addi- tional hardw are and connect it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , a potentiometer f or sim ulated analog input, push-b utton s witches and eight leds connected to por tb . 10.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstr ation board that suppor ts the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers . all the necessar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can prog r am the sample microcontrollers pro vided with the picdem-2 board, on a pr o ma te ii pro- g r ammer or picst ar t - plus , and easily test r mw are . the picmaster em ulator ma y also be used with the picdem-2 board to test r mw are . additional prototype area has been pro vided to the user f or adding addi- tional hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include a rs-232 inter- f ace , push-b utton s witches , a potentiometer f or sim u- lated analog input, a ser ial eepr om to demonstr ate usage of the i 2 c b us and separ ate headers f or connec- tion to an lcd module and a k e ypad. 10.8 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstr ation board that suppor ts the pic16c923 and pic16c924 in the plcc pac kage . it will also suppor t future 44-pin plcc microcontrollers with a lcd module . all the neces- sar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can pro- g r am the sample microcontrollers pro vided with the picdem-3 board, on a pr o ma te ii prog r am- mer or picst ar t plus with an adapter soc k et, and easily test r mw are . the picmaster em ulator ma y also be used with the picdem-3 board to test r m- w are . additional prototype area has been pro vided to the user f or adding hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , push-b utton s witches , a potenti- ometer f or sim ulated analog input, a ther mistor and separ ate headers f or connection to an e xter nal lcd module and a k e ypad. also pro vided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments , that is capab le of displa ying time , temper ature and da y of the w eek. the picdem-3 pro vides an addi- tional rs-232 interf ace and windo ws 3.1 softw are f or sho wing the dem ultiple x ed lcd signals on a pc . a sim- ple ser ial interf ace allo ws the user to constr uct a hard- w are dem ultiple x er f or the lcd signals . 10.9 mplab integrated de velopment en vir onment softwar e the mplab ide softw are br ings an ease of softw are de v elopment pre viously unseen in the 8-bit microcon- troller mar k et. mplab is a windo ws based application which contains: a full f eatured editor three oper ating modes - editor - em ulator - sim ulator a project manager customizab le tool bar and k e y mapping a status bar with project inf or mation extensiv e on-line help mplab allo ws y ou to: edit y our source les (either assemb ly or ?? one touch assemb le (or compile) and do wnload to pic16/17 tools (automatically updates all project inf or mation) deb ug using: - source les - absolute listing le t r ansf er data dynamically via dde (soon to be replaced b y ole) run up to f our em ulators on the same pc the ability to use mplab with microchip s sim ulator allo ws a consistent platf or m and the ability to easily s witch from the lo w cost sim ulator to the full f eatured em ulator with minimal retr aining due to de v elopment tools . 10.10 assemb ler (mp asm) the mp asm univ ersal macro assemb ler is a pc- hosted symbolic assemb ler . it suppor ts all microcon- troller ser ies including the pic12c5xx, pic14000, pic16c5x, pic16cxxx , and pic17cxx f amilies . mp asm off ers full f eatured macro capabilities , condi- tional assemb ly , and se v er al source and listing f or mats . it gener ates v ar ious object code f or mats to suppor t microchip's de v elopment tools as w ell as third par ty prog r ammers . mp asm allo ws full symbolic deb ugging from picmaster, microchip s univ ersal em ulator system.
pic16c71x 1997 microchip technology inc. ds30272a -page 87 mp asm has the f ollo wing f eatures to assist in de v elop- ing softw are f or speci c use applications . pro vides tr anslation of assemb ler source code to object code f or all microchip microcontrollers . macro assemb ly capability . produces all the les (object, listing, symbol, and special) required f or symbolic deb ug with microchip s em ulator systems . suppor ts he x (def ault), decimal and octal source and listing f or mats . mp asm pro vides a r ich directiv e language to suppor t prog r amming of the pic16/17. directiv es are helpful in making the de v elopment of y our assemb le source code shor ter and more maintainab le . 10.11 s oftware sim ulator (mplab-sim) the mplab-sim softw are sim ulator allo ws code de v elopment in a pc host en vironment. it allo ws the user to sim ulate the pic16/17 ser ies microcontrollers on an instr uction le v el. on an y giv en instr uction, the user ma y e xamine or modify an y of the data areas or pro vide e xter nal stim ulus to an y of the pins . the input/ output r adix can be set b y the user and the e x ecution can be perf or med in; single step , e x ecute until break, or in a tr ace mode . m plab-sim fully suppor ts symbolic deb ugging using mplab-c and mp asm. the softw are sim ulator off ers the lo w cost e xibility to de v elop and deb ug code out- side of the labor ator y en vironment making it an e xcel- lent m ulti-project softw are de v elopment tool. 10.12 c compiler ( mplab-c) the mplab-c code de v elopment system is a complete ? compiler and integ r ated de v elopment en vironment f or microchip s pic16/17 f amily of micro- controllers . the compiler pro vides po w erful integ r ation capabilities and ease of use not f ound with other compilers . f or easier source le v el deb ugging, the compiler pro- vides symbol inf or mation that is compatib le with the mplab ide memor y displa y . 10.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic de v elopment tool is a v ail- ab le in tw o v ersions - a lo w cost introductor y v ersion, mp explorer , f or designers to gain a comprehensiv e w or king kno wledge of fuzzy logic system design; and a full-f eatured v ersion, fuzzy tech-mp , edition f or imple- menting more comple x systems . both v ersions include microchip s fuzzy lab ? demon- str ation board f or hands-on e xper ience with fuzzy logic systems implementation . 10.14 mp-drivew a y ? ?application code generator mp-dr iv ew a y is an easy-to-use windo ws-based appli- cation code gener ator . with mp-dr iv ew a y y ou can visually con gure all the per ipher als in a pic16/17 de vice and, with a clic k of the mouse , gener ate all the initialization and man y functional code modules in c language . the output is fully compatib le with micro- chip s mplab-c c compiler . the code produced is highly modular and allo ws easy integ r ation of y our o wn code . mp-dr iv ew a y is intelligent enough to maintain y our code through subsequent code gener ation. 10.15 seev al a ev aluation and pr ogramming system the seev al seepr om designer s kit suppor ts all microchip 2-wire and 3-wire ser ial eepr oms . the kit includes e v er ything necessar y to read, wr ite , er ase or prog r am special f eatures of an y microchip seepr om product including smar t ser ials ? and secure ser ials . the t otal endur ance ? disk is included to aid in tr ade- off analysis and reliability calculations . the total kit can signi cantly reduce time-to-mar k et and result in an optimiz ed system. 10.16 k ee l oq a ev aluation and pr ogramming t ools k ee l oq e v aluation and prog r amming tools suppor t microchips hcs secure data products . the hcs e v al- uation kit includes an lcd displa y to sho w changing codes , a decoder to decode tr ansmissions , and a pro- g r amming interf ace to prog r am test tr ansmitters .
pic16c71x ds30272a -page 88 1997 microchip technology inc. t ab le 10-1: de velopment t ools fr om micr oc hip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c75x 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products picmaster a / picmaster-ce in-circuit emulator 4 4 4 4 4 4 4 4 4 available 3q97 icepic low-cost in-circuit emulator 4 4 4 4 4 4 software tools mplab ? integrated development environment 4 4 4 4 4 4 4 4 4 4 mplab ? c compiler 4 4 4 4 4 4 4 4 4 4 fuzzy tech a -mp explorer/edition fuzzy logic dev. tool 4 4 4 4 4 4 4 4 4 mp-driveway ? applications code generator 4 4 4 4 4 4 total endurance ? software model 4 programmers picstart a lite ultra low-cost dev. kit 4 4 4 4 picstart a plus low-cost universal dev. kit 4 4 4 4 4 4 4 4 4 4 pro mate a ii universal programmer 4 4 4 4 4 4 4 4 4 4 4 4 keeloq a programmer 4 demo boards seeval a designers kit 4 picdem-1 4 4 4 4 picdem-2 4 4 picdem-3 4 keeloq a evaluation kit 4
1997 microchip technology inc. ds30272a -page 89 pic16c71x applicable devices 710 71 711 715 11.0 e lectrical characteristics f or pic16c710 and pic16c711 absolute maxim um ratings ? ambient temper ature under bias ................................................................................................................. -55 to +125?c stor age temper ature .............................................................................................................................. -65?c to +150?c v oltage on an y pin with respect to v ss (e xcept v dd , m clr , and ra4 ) .......................................... -0.3v to ( v dd + 0.3v) v oltage on v dd with respect to v ss ........................................................................................................... -0.3 t o +7.5v v oltage on mclr with respect to v ss ................................................................................................................ 0 to +14v v oltage on ra4 with respect to vss ................................................................................................................... 0 to +14v t otal po w er dissipation (note 1) ............................................................................................................................... . 1.0w maxim um current out of v ss pin ........................................................................................................................... 300 ma maxim um current into v dd pin .............................................................................................................................. 250 ma input clamp current, i ik ( v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maxim um output current sunk b y an y i/o pin .......................................................................................................... 25 ma maxim um output current sourced b y an y i/o pin .................................................................................................... 25 ma maxim um current sunk b y por t a ........................................................................................................................ 200 ma maxim um current sourced b y por t a ................................................................................................................... 200 ma maxim um current sunk b y por tb ........................................................................................................................ 200 ma maxim um current sourced b y por tb ................................................................................................................... 200 ma note 1: p o w er dissipation is calculated as f ollo ws: pdis = v dd x { i dd - ? i oh } + ? {( v dd - v oh ) x i oh } + ? ( v o l x i ol ) t ab le 11-1: cr oss ref erence of de vice specs f or oscillator configurations and frequencies of operation (commer cial de vices) ? no tice: stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . osc pic16c710-04 pic16c711-04 pic16c710-10 pic16c711-10 pic16c710-20 pic16c711-20 pic16lc710-04 pic16lc711-04 pic16c710/jw pic16c711/jw rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5 v i pd : 21 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 m a typ . at 3.0v i pd : 5.0 m a typ . at 3v f req: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 m a typ . at 3.0v i pd : 5.0 m a typ . at 3v f req: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended f or u se in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ . at 5 .5v i dd : 30 ma max. at 5 .5v i dd : 30 ma max. at 5 .5v i dd : 30 ma max. at 5 .5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v f req: 4 mhz max. f req: 10 mhz max. f req: 20 mhz max. f req: 10 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ . at 3 2 khz, 4.0v i pd : 0.9 m a typ . at 4.0v f req: 200 khz max. not recommended f or u se in lp mode not recommended f or u se in lp mode v dd : 2.5v to 6.0v i dd : 48 m a max. at 3 2 khz, 3.0v i pd : 5.0 m a max. at 3.0v f req: 200 khz max. v dd : 2.5v to 6.0v i dd : 48 m a max. at 3 2 khz, 3.0v i pd : 5.0 m a max. at 3 .0v f req: 200 khz max.
pic16c71x ds30272a -page 90 1997 microchip technology inc. applicable devices 710 71 711 715 11.1 dc characteristics: pic16c710-04 (commer cial, industrial, extended ) pic16c711-04 (commer cial, industrial, extended ) pic16c710-10 (commer cial, industrial, extended ) pic16c711-10 (commer cial, industrial, extended ) pic16c710-20 (commer cial, industrial, extended ) pic16c711-20 (commer cial, industrial, extended ) dc chara cteristics standar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) -40?c t a +125?c (e xtended) p aram. no. characteristic sym min t yp? max units conditions d001 d001a supply v oltage v dd 4.0 4.5 - - 6.0 5.5 v v xt , rc and lp osc con gur ation hs osc con gur ation d002* ram data retention v oltage (note 1) v dr - 1.5 - v d003 v dd star t v oltage to ensure inter nal p o w er- on reset signal v por - v ss - v see section on p o w er-on reset f or details d004* v dd r ise r ate to ensure inter nal p o w er-on reset signal s vdd 0.05 - - v/ms see section on p o w er-on reset f or details d005 bro wn-out reset v oltage b vdd 3.7 4.0 4.3 v boden con gur ation bit is enab led 3.7 4.0 4.4 v extended range only d010 d013 supply current (note 2) i dd - - 2.7 13.5 5 30 ma ma xt, rc osc con gur ation f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con gur ation f osc = 20 mhz, v dd = 5.5v d015 bro wn-out reset current (note 5) d i bor - 300* 500 m a bor enab led v dd = 5.0v d020 d021 d021a d021b p o w er-do wn current (note 3) i pd - - - - 10.5 1.5 1.5 1.5 42 21 24 30 m a m a m a m a v dd = 4.0v , wdt enab led, -40 c to +85 c v dd = 4.0v , wdt disab led, -0 c to +70 c v dd = 4.0v , wdt disab led, -40 c to +85 c v dd = 4.0v , wdt disab led, -40 c to +125 c d023 bro wn-out reset current (note 5) d i bor - 300* 500 m a bor enab led v dd = 5.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered w ithout losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current consumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er-do wn current in sleep mode does not depend on the oscillator type . p o w er-do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be esti- mated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm. 5: the d current is the additional current consumed when this per ipher al is enab led. this current should be added to the base i dd or i pd measurement.
1997 microchip technology inc. ds30272a -page 91 pic16c71x applicable devices 710 71 711 715 11.2 dc characteristics: pic16lc710-04 (commer cial, industrial , extended ) pic16lc711-04 (commer cial, industrial , extended ) dc chara cteristics standar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) -40?c t a +125?c (e xtended) p aram no. characteristic sym min t yp? max units conditions d001 supply v oltage commercial/industr ial extended v dd v dd 2.5 3.0 - - 6.0 6.0 v v lp , xt , rc osc con gur ation (dc - 4 mhz) lp , xt , rc osc con gur ation (dc - 4 mhz) d002* ram data retention v oltage (note 1) v dr - 1.5 - v d003 v dd star t v oltage to ensure inter nal p o w er- on reset signal v por - v ss - v see section on p o w er-on reset f or details d004* v dd r ise r ate to ensure inter nal p o w er- on reset signal s vdd 0.05 - - v/ms see section on p o w er-on reset f or details d005 bro wn-out reset v oltage b vdd 3.7 4.0 4.3 v boden con gur ation bit is enab led d010 d010a d015 supply current (note 2) bro wn-out reset current (note 5) i dd d i bor - - - 2.0 22.5 300* 3.8 48 500 ma m a m a xt, rc osc con gur ation f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con gur ation f osc = 32 khz, v dd = 3.0v , wdt disab led bor enab led v dd = 5.0v d020 d021 d021a d021b d023 p o w er-do wn current (note 3) bro wn-out reset current (note 5) i pd d i bor - - - - - 7.5 0.9 0.9 0.9 300* 30 5 5 10 500 m a m a m a m a m a v dd = 3.0v , wdt enab led, -40 c to +85 c v dd = 3.0v , wdt disab led, 0 c to +70 c v dd = 3.0v , wdt disab led, -40 c to +85 c v dd = 3.0v , wdt disab led, -40 c to +125 c bor enab led v dd = 5.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered w ithout losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current consumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er-do wn current in sleep mode does not depend on the oscillator type . p o w er-do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be esti- mated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm. 5: the d current is the additional current consumed when this per ipher al is enab led. this current should be added to the base i dd or i pd measurement.
pic16c71x ds30272a -page 92 1997 microchip technology inc. applicable devices 710 71 711 715 11.3 dc characteristics: pic16c710-04 (commer cial, industrial, extended ) pic16c711-04 (commer cial, industrial, extended ) pic16c710-10 (commer cial, industrial, extended ) pic16c711-10 (commer cial, industrial, extended ) pic16c710-20 (commer cial, industrial, extended ) pic16c711-20 (commer cial, industrial, extended ) pic16lc710-04 (commer cial, industrial, extended ) pic16lc711-04 (commer cial, industrial, extended ) dc chara cteristics standar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) -40?c t a +125?c (e xtended) oper ating v oltage v dd r ange as descr ibed in dc spec section 11.1 and section 11.2 . p aram no. characteristic sym min t yp ? max units conditions input lo w v olta g e i/o por ts v il d030 with ttl b uff er v ss - 0. 1 5 v dd v f or entire v dd r ange d030a v ss - 0.8v v 4.5 v dd 5.5v d031 with schmitt t r igger b uff er v ss - 0.2 v dd v d032 mclr , o sc1 (in rc mode) v ss - 0.2 v dd v d033 osc1 (in xt , hs and lp) v ss - 0.3 v dd v note1 input high v olta g e i/o por ts v ih - d040 with ttl b uff er 2.0 - v dd v 4.5 v dd 5.5v d040a 0. 25 v dd + 0.8v - v dd v f or entire v dd r ange d041 with schmitt t r igger b uff er 0.8 v dd - v dd v f or entire v dd r ange d042 mclr , r b0/int 0.8 v dd - v dd v d042a osc1 (xt , hs and lp) 0.7 v dd - v dd v note1 d043 osc1 (in rc mode) 0. 9v dd - v dd v d070 por tb w eak pull-up current i purb 50 250 400 m a v dd = 5v , v pin = v ss input leaka g e current (notes 2, 3) d060 i/o por ts i il - - 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt , hs and lp osc con gur ation * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic16c7x be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as current sourced b y t he pin.
1997 microchip technology inc. ds30272a -page 93 pic16c71x applicable devices 710 71 711 715 output lo w v olta g e d080 i/o por ts v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v , -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v , -40 c to +125 c d083 osc2/clk out (rc osc con g) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v , -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v , -40 c to +125 c output high v olta g e d090 i/o por ts (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v , -40 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v , -40 c to +125 c d092 osc2/clk out (rc osc con g) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v , -40 c to +85 c d092a v dd - 0.7 - - v i oh = -1.0 ma, v dd = 4.5v , -40 c to +125 c d130 * open-drain high v olta g e v od - - 14 v ra4 pin capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt , hs and lp modes when e xter nal cloc k is used to dr iv e osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf dc chara cteristics standar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) -40?c t a +125?c (e xtended) oper ating v oltage v dd r ange as descr ibed in dc spec section 11.1 and section 11.2 . p aram no. characteristic sym min t yp ? max units conditions * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic16c7x be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as current sourced b y t he pin.
pic16c71x ds30272a -page 94 1997 microchip technology inc. applicable devices 710 71 711 715 11.4 timing p arameter symbology the timing par ameter symbols ha v e been created f ollo wing one of the f ollo wing f or mats: figure 11-1: load conditions 1. tpps2pps 2. tpps t f f requency t time lo w ercase letters (pp) and their meanings: pp cc ccp1 osc osc1 c k clk out rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o por t t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-impedance) v v alid l lo w z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf f or all pins e xcept osc2 15 pf f or osc2 output load condition 1 load condition 2
1997 microchip technology inc. ds30272a -page 95 pic16c71x applicable devices 710 71 711 715 11.5 timing dia grams and speci cations figure 11-2: external cloc k timing t ab le 11-2: external cloc k timing requirements p arameter no. sym characteristic min t yp? max units conditions f os c external clkin frequenc y (note 1) dc 4 mhz xt osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequenc y (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 5 20 200 m h z khz h s osc mode lp osc mode 1 t osc external clkin p eriod (note 1) 250 ns xt osc mode 250 ns hs osc mod e (-04) 100 ns hs osc mod e (-10) 50 ns hs osc mod e (-20) 5 m s lp osc mode oscillator p eriod (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mod e (-04) 10 0 50 25 0 250 n s ns hs osc mod e (-10) hs osc mod e (-20) 5 m s lp osc mode 2 t cy instruction cyc le time (note 1) 200 dc ns t cy = 4/ f osc 3 t osl, t osh external cloc k in (osc1) high or lo w time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 t osr, t osf external cloc k in (osc1) rise or f all time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time-base per iod. all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating conditions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current consumption. all de vices are tested to oper ate at "min." v alues with an e xter nal cloc k applied to the osc1/clkin pin. when an e xter nal cloc k input is used, the "max." cycle time limit is "dc" (no cloc k) f or all de vices . osc2 is disconnected (has no loading) f or the pic16c710/711. osc1 clk out q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
pic16c71x ds30272a -page 96 1997 microchip technology inc. applicable devices 710 71 711 715 figure 11-3: clk o ut and i/o timing t ab le 11-3: clk out and i/o timing requirements p arameter no. sym characteristic min t yp? max units conditions 10* t osh2c kl osc1 - to clk out 15 30 ns note 1 11* t osh2c kh osc1 - to clk out - 15 30 ns note 1 12* tc kr clk out r ise time 5 15 ns note 1 13* tc kf clk out f all time 5 15 ns note 1 14* tc kl2iov clk out to p or t out v alid 0.5 t cy + 20 ns note 1 15* tiov2c kh p or t in v alid bef ore clk out - 0.25 t cy + 25 ns note 1 16* tc kh2ioi p or t in hold after clk out - 0 ns note 1 17* t osh2iov osc1 - (q1 cycle) to p or t out v alid 80 - 100 ns 18* t osh2ioi osc1 - (q2 cycle) to p or t input in v alid (i/o in hold time) tbd ns 19* tiov2osh p or t input v alid to osc1 - (i/o in setup time) tbd ns 20* tior p or t output r ise time pic16 c 710/711 10 25 ns pic16 lc 710/711 60 ns 21* tiof p or t output f all time pic16 c 710/711 10 25 ns pic16 lc 710/711 60 ns 22??* tinp int pin high or lo w time 20 ns 23??* t rbp rb7:rb4 change int high or lo w time 20 ns * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. ?? these par ameters are asynchronous e v ents not related to an y inter nal cloc k edges . note 1: measurements are tak en in rc mode where clk out output is 4 x t osc . note: ref er to figure 11-1 f or load conditions . osc1 clk out i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old v alue ne w v alue
1997 microchip technology inc. ds30272a -page 97 pic16c71x applicable devices 710 71 711 715 figure 11-4: reset, w atc hdog timer , oscillator star t-up timer and p o wer -up timer timing figure 11-5: br o wn-out rese t timing t ab le 11-4: reset, w atc hdog timer , oscillator star t-up timer , p o wer -up timer , and br o wn-out reset r equirements p arameter no. sym characteristic min t yp? max units conditions 30 tmcl mclr pulse width (lo w) 1 m s v dd = 5v , -40?c to +125?c 31 t wdt w atchdog timer time-out p er iod (no prescaler) 7* 18 33* ms v dd = 5v , -40?c to +125?c 32 t ost oscillation star t-up timer p er iod 1024 t osc t osc = osc1 per iod 33 tpwr t p o w er up timer p er iod 28* 72 132* ms v dd = 5v , -40?c to +125?c 34 t ioz i/o hi-impedance from mclr lo w or w atchdog timer reset 1.1 m s 35 t bor bro wn-out reset pulse width 100 m s 3.8v v dd 4.2v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. v dd mclr inter nal por pwr t time-out osc time-out inter nal reset w atchdog timer reset 33 32 30 31 34 i/o pins 34 note: ref er to figure 11-1 f or load conditions . v dd bv dd 35
pic16c71x ds30272a -page 98 1997 microchip technology inc. applicable devices 710 71 711 715 figure 11-6: timer0 external cl oc k timings t ab le 11-5: timer0 external cloc k requirements p aram no. sym characteristic min t yp? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ns must also meet par ameter 42 with prescaler 10* ns 41 tt0l t0cki lo w pulse width no prescaler 0.5 t cy + 20* ns must also meet par ameter 42 with prescaler 10* ns 42 tt0p t0cki p er iod greater of: 20 ns or t cy + 40 * n ns n = prescale v alue ( 2 , 4,..., 256) 48 tc k e2tmri dela y from e xter nal cloc k edge to timer increment 2t osc 7t osc * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note: ref er to figure 11-1 f or load conditions . 41 42 40 ra4/t0cki tmr0
1997 microchip technology inc. ds30272a -page 99 pic16c71x applicable devices 710 71 711 715 t ab le 11-6: a/d con ver ter characteristics: pic16c710 /711 -04 (commer cial, industrial, extended ) pic16c710 /711 -10 (commer cial, industrial, extended ) pic16c710/711-20 (commercial, industrial, extended ) p ic16 l c710 /711 - 04 ( commer cial, industrial, extended ) p ara m n o. sym characteristic min t yp? max units conditions a01 n r resolution 8-bits bit v ref = v dd , v ss ain v ref a02 e abs absolute error < 1 lsb v ref = v dd , v ss ain v ref a03 e il integ r al linear ity error < 1 lsb v ref = v dd , v ss ain v ref a04 e dl diff erential linear ity error < 1 lsb v ref = v dd , v ss ain v ref a05 e fs full scale error < 1 lsb v ref = v dd , v ss ain v ref a06 e o ff offset error < 1 lsb v ref = v dd , v ss ain v ref a10 monotonicity guar anteed v ss v ain v ref a20 v ref ref erence v oltage 2.5v v dd + 0.3 v a25 v ain analog input v oltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of a nalog v oltage source 10.0 k w a40 i ad a/d con v ersion current ( v dd ) 180 m a a v er age current consumption w he n a /d is on. (note 1) a50 i ref v ref input current (note 2) 10 1 000 10 m a m a dur ing v ain acquisition. based on diff erential of v hold to v ain . t o charge c hold see section 7.1 . dur ing a/d con v ersion cycle * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated . t hese par ameters are f or design guidance only and are not tested. note 1: when a/d is off , it will not consume an y current other than minor leakage current. t he po w er-do wn current spec includes an y such leakage from the a/d module . 2: v ref current is from ra3 pin or v dd pin, whiche v er is selected as ref erence input.
pic16c71x ds30272a -page 100 1997 microchip technology inc. applicable devices 710 71 711 715 figure 11-7: a /d con ver sion timing t ab le 11-7: a/d con ver sion requirements p aram no. sym characteristic min t yp? max units conditions 13 0 t ad a/d cloc k per io d pic16 c 710/711 1. 6 m s t osc based , v ref 3 3.0 v pic16 lc 710/711 2.0 m s t osc based, v ref full r ange pic16 c 710/711 2.0* 4.0 6.0 m s a/d rc mode pic16 lc 710/711 3.0* 6.0 9.0 m s a/d rc mode 131 t cnv con v ersion time ( not including s/h time). ( note 1 ) 9.5 t ad 132 t acq acquisition time note 2 5* 20 m s m s the minim um time is the ampli er settling time . this ma y be used if the "ne w" input v oltage has not changed b y more than 1 lsb (i.e ., 19.5 mv @ 5.12v) from the last sampled v oltage (as stated on c hold ). 134 t go q4 to ad cloc k star t t osc /2 if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 135 t swc switching from con v er t ? sample time 1.5 t ad * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. this speci cation ensured b y design. note 1: adres register ma y be read on the f ollo wing t cy cycle . 2: see section 7.1 f or min conditions . 131 130 132 bsf adcon 0 , go q4 a/d clk a/d d a t a adres adif go sample old_d a t a sampling st opped done new_d a t a (t osc /2) (1) 7 6 5 4 3 2 1 0 note 1: if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 1 tcy
1997 microchip technology inc. ds30272a -page 101 pic16c71x applicable devices 710 71 711 715 12.0 dc and a c characteristics graphs and t ab les f or pic16c710 and pic16c711 the g r aphs and tab les pro vided in this section are f or design guidance and are not tested or guar anteed. in some graphs or tab les the data presented are outside speci ed operating rang e (i.e ., outside speci ed v dd rang e). this is f or inf ormation onl y and de vices are guaranteed to operate pr operl y onl y within the speci ed rang e . figure 12-1: t ypical i pd vs. v dd (wdt disab led, rc mode) figure 12-2: maxim um i pd vs. v dd (wdt disab led, rc mode) note: the data presented in this section is a statistical summar y of data collected on units from diff erent lots o v er a per iod of time and matr ix samples . 't ypical' represents the mean of the distr ib ution at, 25 c , while 'max' or 'min' represents (mean +3 s ) and (mean -3 s ) respectiv ely where s is standard de viation. 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (v olts) i pd ( m a) v dd (v olts) 10.000 1.000 0.100 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 85 c 70 c 25 c 0 c -40 c
pic16c71x ds30272a -page 102 1997 microchip technology inc. applicable devices 710 71 711 715 figure 12-3: t ypical i pd vs. v dd @ 25 c (wdt enab led, rc mode) figure 12-4: maxim um i pd vs. v dd (wdt enab led, rc mode) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (v olts) 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (v olts) -40 c 0 c 70 c 85 c figure 12-5: t ypical rc oscillator frequenc y vs. v dd figure 12-6: t ypical rc oscillator frequenc y vs. v dd figure 12-7: t ypical rc oscillator frequenc y vs. v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 fosc(mhz) ce xt = 22 pf , t = 25 c r = 100k r = 10k r = 5k shaded area is be y ond recommended r ange . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 fosc(mhz) ce xt = 100 pf , t = 25 c r = 100k r = 10k r = 5k r = 3.3k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 1000 900 800 700 600 500 400 300 200 100 0 fosc(khz) ce xt = 300 pf , t = 25 c r = 3.3k r = 5k r = 10k r = 100k
1997 microchip technology inc. ds30272a -page 103 pic16c71x applicable devices 710 71 711 715 figure 12-8: t ypical i pd vs. v dd br o wn- out detect enab led (rc mode) figure 12-9: maxim um i pd vs. v dd br o wn-out detect enab led (85 c to -40 c, rc mode) the shaded region represents the b uilt-in h ysteresis of the bro wn-out reset circuitr y . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (v olts) i pd ( m a) de vice in bro wn-out de vice no t in bro wn-out reset reset the shaded region represents the b uilt-in h ysteresis of the bro wn-out reset circuitr y . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (v olts) i pd ( m a) 4.3 1600 de vice no t in bro wn-out reset de vice in bro wn-out reset figure 12-10: t ypical i pd vs. timer1 enab led (32 k h z , rc0/rc1 = 33 p f/33 p f , rc mode) figure 12-11: maxim um i pd vs. timer1 enab led (32 k h z , rc0/rc1 = 33 p f/33 p f , 85 c to -40 c, rc mode) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) i pd ( m a) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) i pd ( m a) 35 40 45
pic16c71x ds30272a -page 104 1997 microchip technology inc. applicable devices 710 71 711 715 figure 12-12: t ypical i dd vs. frequenc y (rc mode @ 22 p f , 25 c) figure 12-13: maxim um i dd vs. frequenc y (rc mode @ 22 p f , -40 c to 85 c) 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 f requency(mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v be y ond recommended r ange 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 f requency(mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v be y ond recommended r ange
1997 microchip technology inc. ds30272a -page 105 pic16c71x applicable devices 710 71 711 715 figure 12-14: t ypical i dd vs. frequenc y (rc mode @ 100 p f , 25 c) figure 12-15: maxim um i dd vs. frequenc y (rc mode @ 100 p f , -40 c to 85 c) 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 f requency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is be y ond recommended r ange 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 f requency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is be y ond recommended r ange
pic16c71x ds30272a -page 106 1997 microchip technology inc. applicable devices 710 71 711 715 figure 12-16: t ypical i dd vs. frequenc y (rc mode @ 300 p f , 25 c) figure 12-17: maxim um i dd vs. frequenc y (rc mode @ 300 p f , -40 c to 85 c) 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 f requency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 f requency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
1997 microchip technology inc. ds30272a -page 107 pic16c71x applicable devices 710 71 711 715 figure 12-18: t ypical i dd vs . capacitance @ 500 k h z (rc mode) t ab le 12-1: rc oscillator frequencies ce xt re xt a vera g e fosc @ 5v , 25 c 22 pf 5k 4.12 mhz 1.4% 10k 2.35 mhz 1.4% 100k 268 khz 1.1% 100 pf 3.3k 1.80 mhz 1.0% 5k 1.27 mhz 1.0% 10k 688 khz 1.2% 100k 77.2 khz 1.0% 300 pf 3.3k 707 khz 1.4% 5k 501 khz 1.2% 10k 269 khz 1.6% 100k 28.3 khz 1.1% the percentage v ar iation indicated here is par t to par t v ar iation due to nor mal process distr ib ution. the v ar iation indicated is 3 standard de viation from a v er age v alue f or v dd = 5v . capacitance(pf) 600 i dd ( m a) 500 400 300 200 100 0 20 pf 100 pf 300 pf 5.0v 4.0v 3.0v figure 12-19: t ransconductance( gm ) of hs oscillator vs. v dd figure 12-20: t ransconductance( gm ) of lp oscillator vs. v dd figure 12-21: t ransconductance( gm ) of xt oscillator vs. v dd 4.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (v olts) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 max -40 c t yp 25 c min 85 c shaded area is be y ond recommended r ange 110 100 90 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (v olts) max -40 c t yp 25 c min 85 c shaded area s are be y ond recommended r ange 1000 900 800 700 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (v olts) max -40 c t yp 25 c min 85 c shaded area s are be y ond recommended r ange
pic16c71x ds30272a -page 108 1997 microchip technology inc. applicable devices 710 71 711 715 figure 12-22: t ypical xt al star tup time vs. v dd (lp mode , 25 c) figure 12-23: t ypical xt al star tup time vs. v dd (hs mode , 25 c) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) star tup time(seconds) 32 khz, 33 pf/33 pf 200 khz, 15 pf/15 pf 7 6 5 4 3 2 1 4.0 4.5 5.0 5.5 6.0 v dd (v olts) star tup time(ms) 20 mhz, 33 pf/33 pf 8 mhz, 33 pf/33 pf 8 mhz, 15 pf/15 pf 20 mhz, 15 pf/15 pf figure 12-24: t ypical xt al star tup time vs . v dd (xt mode , 25 c) t ab le 12-2: capacitor selection f or cr ystal oscillator s osc t ype cr ystal freq cap. rang e c1 cap. rang e c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf cr ystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm 70 60 50 40 30 20 10 0 3.0 3.5 2.5 4.0 5.0 5.5 6.0 4.5 v dd (v olts) star tup time(ms) 200 khz, 68 pf/68 pf 200 khz, 47 pf/47 pf 1 mhz, 15 pf/15 pf 4 mhz, 15 pf/15 pf
1997 microchip technology inc. ds30272a -page 109 pic16c71x applicable devices 710 71 711 715 figure 12-25: t ypical i dd vs. frequenc y (lp mode , 25 c) figure 12-26: maxim um i dd vs. frequenc y (lp mode , 85 c to -40 c) 120 100 80 60 40 20 0 0 50 100 150 200 f requency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 120 100 80 60 40 20 0 0 50 100 150 200 f requency(khz) i dd ( m a) 140 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v figure 12-27: t ypical i dd vs . frequenc y (xt mode , 25 c) figure 12-28: maxim um i dd vs . frequenc y (xt mode , -40 c to 85 c) 1200 1000 800 600 400 200 0 0.0 0.4 f requency(mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0.0 0.4 f requency(mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
pic16c71x ds30272a -page 110 1997 microchip technology inc. applicable devices 710 71 711 715 figure 12-29: t ypical i dd vs . frequenc y (hs mode , 25 c) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 2 4 6 8 10 12 14 16 18 20 f requency(mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v figure 12-30: maxim um i dd vs . frequenc y (hs mode , -40 c to 85 c) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 2 4 6 8 10 12 14 16 18 20 f requency(mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v
1997 microchip technology inc. ds30272a -page 111 pic16c71x applicable devices 710 71 711 715 13.0 e lectrical characteristics f or pic16c 715 absolute maxim um ratings ? ambie nt temper ature under bias ................................................................................................................ . -55 to +125?c sto r age temper ature .............................................................................................................................. -65?c to +150?c v olt a ge on an y pin with respect to v ss ( e xcept v dd and mclr ) .................................................... -0.3v to ( v dd + 0.3v) v o lt age on v dd with respect to v ss ................................................................................................................ 0 to +7.5v v olt a ge on mclr w ith respect to v ss ................................................................................................................ 0 to +14v v oltage on ra4 with respect to vss ................................................................................................................... 0 to +14v t ot a l po w er dissipation (note 1) ............................................................................................................................... . 1.0w ma x im um current out of v ss pin ........................................................................................................................... 300 m a m a xim um current into v dd pin .............................................................................................................................. 250 m a input clamp current, i ik ( v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma ma x im um output current sunk b y an y i/o pin .......................................................................................................... 25 ma ma x im um output current sourced b y an y i/o pin .................................................................................................... 2 5 m a m a xim um current sunk b y por t a ........................................................................................................................ 200 m a maxi m um current sourced b y por t a ................................................................................................................... 200 ma maxim um current sunk b y por tb ........................................................................................................................ 200 ma maxim um current sourced b y por tb ................................................................................................................... 200 ma note 1: p o w er dissipation is calculated as f ollo ws: pdis = v dd x { i dd - ? i oh } + ? {( v dd - v oh ) x i oh } + ? ( v o l x i ol ) . ? no tice: s tresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . t his is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation listings of this speci cation is not implied. e xposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability .
pic16c71x ds30272a -page 112 1997 microchip technology inc. applicable devices 710 71 711 715 t ab le 13-1: cr oss ref erence of de vice specs f or oscillator configurations and frequencies of operation (commer cial de vices ) osc pic16c715-04 pic16c715-10 pic16c715-20 pic16lc715-04 pic16c715/jw rc v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 5.5v i dd : 2.0 ma typ . at 3.0v i pd : 0.9 m a typ . at 3v f req: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. xt v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 5.5v i dd : 2.0 ma typ . at 3.0v i pd : 0.9 m a typ . at 3v f req: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v do not use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ . at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v f req: 4 mhz max. f req: 10 mhz max. f req: 20 mhz max. f req: 10 mhz max. lp v dd : 4.0v to 5.5v i dd : 52.5 m a typ . at 32 khz, 4.0v i pd : 0.9 m a typ . at 4.0v f req: 200 khz max. do not use in lp mode do not use in lp mode v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v f req: 200 khz max. v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v f req: 200 khz max. the shaded sections indicate oscillator selections which are tested f or functionality , b ut not f or min/max speci cations . it is recommended that the user select the de vice type that ensures the speci cations required.
1997 microchip technology inc. ds30272a -page 113 pic16c71x applicable devices 710 71 711 715 13.1 dc characteristics: pic16c715-04 (commer cial, industrial, extended) pic16c715-10 (commer cial, industrial, extended) pic16c715-20 (commer cial, industrial, extended)) d c chara cteristics standar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) -40?c t a +125?c (e xtended) p aram. no. characteristic sym min t yp? max units conditions d001 d001a supply v oltage v dd 4. 0 4.5 - - 5.5 5.5 v v xt , rc and lp osc con gur atio n hs osc con gur ation d002 * ram data retention v oltage (note 1) v dr - 1.5 - v de vice in sleep mode d003 v dd s tar t v oltage to ensure i nter nal p o w er- on reset signal v por - v ss - v see section on p o w er-on re set f or details d004 * v dd r ise r ate to ensure i nter nal p o w er-on re set signal s vdd 0.05 - - v/ms see section on p o w er-on res et f or details d005 bro wn-out reset v oltage b vdd 3. 7 4.0 4. 3 v boden con gur ation bit is enab led d010 d 01 3 supply current (note 2 ) i dd - - 2.7 1 3. 5 5 3 0 ma m a xt, rc osc con gur ation (pic16c715-04) f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con gur ation (pic16c715-20) f osc = 20 mhz, v dd = 5.5 v d015 bro wn-out reset current (note 5) d i bor - 300 * 50 0 m a bor enab led v dd = 5.0v d020 d021 d021a d021b p o w er -do wn current (note 3) i pd - - - - 10.5 1. 5 1. 5 1. 5 42 21 24 30 m a m a m a m a v dd = 4.0v , wdt enab led, -40 c to +85 c v dd = 4.0v , wdt disab led, -0 c to +70 c v dd = 4.0v , wdt disab led, -40 c to +85 c v dd = 4.0v , wdt disab led, -40 c to +125 c d023 bro wn-out reset current (note 5) d i bor - 300 * 50 0 m a bor enab led v dd = 5.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . o ther f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current c onsumption. the test conditions f or all i dd m easurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins t r istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er -d o wn current in sleep mode does not depend on the oscillator type . p o w er -d o wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: f or rc osc con gur ation, current through re xt is not included. t he current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm. 5: the d current is the additional current consumed when this per ipher al is e nab led. this current should be added to the base i dd or i pd measurement.
pic16c71x ds30272a -page 114 1997 microchip technology inc. applicable devices 710 71 711 715 13.2 dc characteristics: pic16lc715-04 (commer cial, industrial) d c chara cteristics standar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) p aram no. characteristic sym min t yp? max units conditions d001 supply v oltage v dd 2.5 - 5.5 v l p , x t , rc osc con gur ation (dc - 4 mhz) d002 * ram data retention v oltage (note 1) v dr - 1.5 - v de vice in sleep mode d003 v dd star t v oltage to ensure inter nal p o w er-on res et signal v por - v ss - v see section on p o w er-on res et f or details d004 * v dd r ise r ate to ensure inter nal p o w er- on res et signal s vdd 0.05 - - v/ms see section on p o w er-on res et f or details d005 bro wn-out reset v oltage b vdd 3. 7 4.0 4. 3 v boden con gur ation bit is enab led d010 d010a supply current ( note 2) i dd - - 2.0 22.5 3.8 48 ma m a xt, rc osc con gur ation f osc = 4 mhz, v dd = 3.0v (note 4 ) lp osc con gur ation f osc = 32 kh z, v dd = 3.0v , wdt disab led d015 bro wn-out reset current (note 5 ) d i bor - 300 * 50 0 m a bor enab led v dd = 5 .0v d020 d021 d021a p o w er -do wn current (note 3) i pd - - - 7. 5 0. 9 0. 9 30 5 5 m a m a m a v dd = 3.0v , wdt enab led, -40 c to +85 c v dd = 3.0v , wdt disab led, 0 c to +70 c v dd = 3.0v , wdt disab led, -40 c to +85 c d023 bro wn-out reset current (note 5 ) d i bor - 300 * 50 0 m a bor enab led v dd = 5 .0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . o ther f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current c onsumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins t r istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er -d o wn current in sleep mode does not depend on the oscillator type . p o w er -d o wn current is measured with the par t in sleep mode , with all i/o pins in hi-imped an ce state and tied to v dd and v ss . 4: f or rc osc con gur ation, current through re xt is not included. t he current through the resistor can be esti- mated b y the f or m ula i r = v dd /2re xt ( ma) with re xt i n kohm . 5: the d current is the additional current consumed when this per ipher al is e nab led. this current should be added to the base i dd or i pd measurement.
1997 microchip technology inc. ds30272a -page 115 pic16c71x applicable devices 710 71 711 715 13.3 dc characteristics: pic16c715-04 (commer cial, industrial, extended) pic16c715-10 (commer cial, industrial, extended) pic16c715-20 (commer cial, industrial, extended) pic16lc715-04 (commer cial, industrial)) d c chara cteristics s tandar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) -40?c t a +125?c (e xtended) oper ating v oltage v dd r ange as descr ibed in dc spec section 13.1 and section 13.2 . p aram no. characteristic sym min t yp ? max units conditions input lo w v olta g e i/o por ts v il d030 with ttl b uff er v ss - 0. 5 v v d031 with schmitt t r igger b uff er v ss - 0.2 v dd v d032 mclr , ra4/t0cki,osc1 ( in rc mode) v ss - 0.2 v dd v d033 osc1 (in xt , hs and lp) v ss - 0.3 v dd v note1 input high v olta g e i/o por ts v ih - d040 with ttl b uff er 2.0 - v dd v 4.5 v dd 5.5v d040a 0. 8 v dd - v dd v f or v dd > 5.5v or v dd < 4.5v d041 with schmitt t r igger b uff er 0.8 v dd - v dd v f or entire v dd r ange d042 mclr , ra4/t0cki rb0 /i nt 0.8 v dd - v dd v d042a o sc1 (xt , hs and lp) 0.7 v dd - v dd v note1 d043 osc1 (in rc mode) 0. 9v dd - v dd v d070 por tb w eak pull-up current i purb 50 250 4 00 m a v dd = 5v , v pin = v ss input leaka g e current (notes 2, 3) d060 i/o por ts i il - - 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt , hs and lp osc con gur ation output lo w v olta g e d080 i/o por ts v ol - - 0.6 v i ol = 8.5 ma, v dd = 4 .5v , - 40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4 .5v , - 40 c to +125 c d083 osc2/clk out (rc osc con g) - - 0.6 v i ol = 1.6 ma, v dd = 4 .5v , - 40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4 .5v , - 40 c to +125 c ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1 /clkin pin is a schmitt t r igger input. i t is not recommended that the pic16c7 x b e dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as coming out of the pin .
pic16c71x ds30272a -page 116 1997 microchip technology inc. applicable devices 710 71 711 715 output high v olta g e d090 i/o por ts (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v , - 40 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v , -40 c to +125 c d092 osc2/clk out (rc osc con g) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v , - 40 c to +85 c d092a v dd - 0.7 - - v i oh = -1.0 ma, v dd = 4.5v , - 40 c to +125 c capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt , hs and lp modes when e xter nal cloc k is used to dr iv e osc1. d101 all i/o pins and osc2 (in rc mode ) c i o - - 5 0 p f d c chara cteristics s tandar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) -40?c t a +125?c (e xtended) oper ating v oltage v dd r ange as descr ibed in dc spec section 13.1 and section 13.2 . p aram no. characteristic sym min t yp ? max units conditions ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1 /clkin pin is a schmitt t r igger input. i t is not recommended that the pic16c7 x b e dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as coming out of the pin .
1997 microchip technology inc. ds30272a -page 117 pic16c71x applicable devices 710 71 711 715 13.4 timing p arameter symbology the timing par ameter symbols ha v e been created f ollo wing one of the f ollo wing f or mats: figure 13-1: load conditions 1. tpps2pps 2. tpps t f f requency t time lo w ercase letters ( pp) and their meanings: pp cc ccp1 os c osc1 c k clk out rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o por t t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-imped a nce) v v alid l lo w z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 p f f or all pins e xcept osc 2 15 pf f or osc2 output load condition 1 load condition 2
pic16c71x ds30272a -page 118 1997 microchip technology inc. applicable devices 710 71 711 715 13.5 t iming dia grams and speci cations figure 13-2: external cloc k timing t ab le 13-2: cloc k timing requirements p arameter no. sym characteristic min t yp? max units conditions f os external clkin frequenc y (note 1) dc 4 mhz xt osc mode dc 4 mhz hs osc mode ( pic16c 715 -04) dc 20 mhz hs osc mode ( pic16c 715 -20) dc 200 kh z lp osc mode oscillator frequenc y (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 4 mhz hs osc mode ( pic16c 715 -04) 4 4 5 10 20 200 mhz mhz khz hs osc mode ( pic16c 715 -10) hs osc mode (pic16c 715 -20) lp osc mode 1 t os c external clkin p eriod (note 1) 250 ns xt osc mode 250 ns hs osc mode ( pic16c 715 -04) 100 n s hs osc mode ( pic16c 715 -10) 50 ns hs osc mode (pic16c 715 -20) 5 m s lp osc mode oscillator p eriod (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode ( pic16c 715 -04) 100 50 250 250 ns ns hs osc mode ( pic16c 715 -10) hs osc mode (pic16c 715 -20) 5 m s lp osc mode 2 t cy instruction cyc le time (note 1) 200 dc ns t cy = 4/ f osc 3 t osl, t osh external c loc k in (osc1) high or lo w time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 t osr, t osf external cloc k in (osc1) rise or f all time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time -b ase per iod. a ll speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating conditions with the de vice e x ecuting code . e xceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current con- sumption. a ll de vices are tested to oper ate at "min." v alues with an e xter nal cloc k applied to the osc1 /clkin pin. when an e xter nal cloc k input is used, the "max." cycle time limit is "dc" (no cloc k) f or all de vices . osc2 is disconnected (has no loading) f or the pic16c 715 . osc1 clk out q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
1997 microchip technology inc. ds30272a -page 119 pic16c71x applicable devices 710 71 711 715 figure 13-3: c lk o ut and i/o timing t ab le 13-3: clk out and i/o timing requirements p arameter no. sym characteristic min t yp? max units conditions 10 * t osh2c kl osc1 - to clk out 15 30 ns note 1 11 * t osh2c kh osc1 - to clk out - 15 30 ns note 1 12 * tc kr clk out r ise time 5 15 ns note 1 13 * tc kf clk out f all time 5 15 ns note 1 14 * tc kl2iov clk out to p or t out v alid 0.5 t cy + 20 ns note 1 15 * tiov2c kh p or t in v alid bef ore clk out - 0.25 t cy + 25 ns note 1 16 * tc kh2ioi p or t in hold after clk out - 0 ns note 1 17 * t osh2iov osc1 - (q1 cycle) to p or t out v alid 80 - 100 ns 18 * t osh2ioi osc1 - (q2 cycle) to p or t input i n v ali d ( i/o in hold time) tbd ns 19 * tiov2osh p or t input v alid to osc1 - (i/o in setup time) tbd ns 20 * tior p or t output r ise time pic16c 715 10 25 ns pic16lc 715 60 ns 21 * tiof p or t output f all time pic16c 715 10 25 ns pic16lc 715 60 ns 22?? * tinp int pin high or lo w time 20 ns 23?? * t rbp rb 7 : rb 4 c hange int high or lo w time 20 ns * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. ?? these par ameters are asynchronous e v ents not related to an y inter nal cloc k edges . note 1: measurements are tak en in rc mode where clk out output is 4 x t osc . note: ref er to figure 13-1 f or load conditions . osc1 clk out i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old v alue ne w v alue
pic16c71x ds30272a -page 120 1997 microchip technology inc. applicable devices 710 71 711 715 figure 13-4: r eset, w atc hdog timer , oscillator star t-up timer , and p o wer -up timer timing figure 13-5: br o wn-out reset timing t ab le 13-4: reset, w atc hdog timer , oscillator star t-up timer , p o wer -up timer , and br o wn-out reset requirements p arameter no. sym characteristic min t yp? max units conditions 30 tmcl mclr pulse width (lo w) 2 m s v dd = 5v , -40?c to +125?c 31* t wdt w atchdog timer time-out p er iod (no prescaler) 7 18 33 ms v dd = 5v , -40?c to +125?c 32 t ost oscillation star t-up timer p er iod 1024 t osc t osc = osc1 per iod 33* tpwr t p o w er up timer p er iod 28 72 132 ms v dd = 5v , -40?c to +125?c 34 t ioz i/o hi -im pedance from mclr lo w or w atchdog timer reset 2 .1 m s 35 t bor bro wn-out reset pulse width 100 m s v dd b vdd (d005) 36 t per p ar ity error reset tbd m s * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. v dd mclr inter nal por pwr t timeout osc timeout inter nal reset w atchdog timer reset 33 32 30 31 34 i/o pins 34 p ar ity error reset 3 6 v dd bv dd 35
1997 microchip technology inc. ds30272a -page 121 pic16c71x applicable devices 710 71 711 715 figure 13-6: timer0 cl oc k timings t ab le 13-5: timer0 cloc k requirements p aram n o. sym characteristic min t yp? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki lo w pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki p er iod greater of: 20 m s or t cy + 40 * n ns n = prescale v alue ( 1, 2, 4, . .., 256) 48 tc k e2tmri dela y from e xter nal cloc k edge to timer increment 2t osc 7t osc * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note: ref er to figure 13-1 f or load conditions . 41 42 40 ra4/t0cki tmr 0
pic16c71x ds30272a -page 122 1997 microchip technology inc. applicable devices 710 71 711 715 t ab le 13-6: a/d con ver ter characteristics: pic16c715-04 (commer cial, industrial, extended) pic16c715-10 (commer cial, industrial, extended) pic16c715-20 (commer cial, industrial, extended) p arameter no. sym characteristic min t yp? max units conditions n r resolution 8 -b its v ref = v dd , v ss a in v ref n int integ r al error less than 1 lsb v ref = v dd , v ss a in v ref n dif diff erential error less than 1 lsb v ref = v dd , v ss a in v ref n fs full scale error less than 1 lsb v ref = v dd , v ss a in v ref n off offset error less than 1 lsb v ref = v dd , v ss a in v ref monotonicity guar anteed v ss a in v ref v ref ref erence v oltage 2.5v v dd + 0.3 v v ain analog input v oltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of analog v oltage source 10.0 k w i ad a/d con v ersion cur- rent ( v dd ) 180 m a a v er age current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 10 ma m a dur ing sampling all other times * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: when a/d is off , it will not consume an y current other than minor leakage current. t he po w er -d o wn current spec includes an y such leakage from the a/d module . 2: v ref current is from ra3 pin or v dd pin, whiche v er is selected as ref erence input.
1997 microchip technology inc. ds30272a -page 123 pic16c71x applicable devices 710 71 711 715 t ab le 13-7: a/d con ver ter characteristics: pic16lc715-04 (commer cial, industrial) p arameter no. sym characteristic min t yp? max units conditions n r resolution 8 -b its v ref = v dd , v ss a in v ref n int integ r al error less than 1 l sb v ref = v dd , v ss a in v ref n dif diff erential error less than 1 l sb v ref = v dd , v ss a in v ref n fs full scale error less than 1 l sb v ref = v dd , v ss a in v ref n off offset error less than 1 l sb v ref = v dd , v ss a in v ref monotonicity guar anteed v ss a in v ref v ref ref erence v oltage 2.5v v dd + 0.3 v v ain analog input v oltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of ana- log v oltage source 10.0 k w i ad a/d con v ersion cur- rent ( v dd ) 90 m a a v er age current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 10 ma m a dur ing sampling all other times * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: when a/d is off , it will not consume an y current other than minor leakage current. the po w er-do wn current spec includes an y such leakage from the a/d module . 2: v ref current is from ra3 pin or v dd pin, whiche v er is selected as ref erence input.
pic16c71x ds30272a -page 124 1997 microchip technology inc. applicable devices 710 71 711 715 figure 13-7: a/d con ver sion timing t ab le 13-8: a/d con ver sion requirements p arameter no. sym characteristic min t yp? max units conditions 130 t ad a/d cloc k per iod 1.6 2.0 m s m s v ref 3 3.0v v ref full r ange 130 t ad a/d inter nal rc oscillator source adcs1 :adcs0 = 11 ( rc oscillator source) 3.0 6.0 9.0 m s pic16lc715, v dd = 3.0v 2.0 4.0 6.0 m s pic16c 715 131 t cnv con v ersion time (not including s/h time). note 1 9.5 t ad 132 t acq acquisition time note 2 20 m s * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: adres register ma y be read on the f ollo wing t cy cycle . 131 130 132 bsf adcon 0 , go q4 a/d clk a/d d a t a adres adif go sample old_d a t a sampling st opped done new_d a t a ( t o sc /2) (1) 7 6 5 4 3 2 1 0 note 1: if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 1 tcy
1997 microchip technology inc. ds30272a -page 125 pic16c71x applicable devices 710 71 711 715 14.0 dc and a c characteristics graphs and t ab les f or pic16c715 the g r aphs and tab les pro vided in this section are f or design guidance and are not tested or guar anteed. in some graphs or tab les the data presented are outside speci ed operating rang e (i.e ., outside speci ed v dd rang e). this is f or inf ormation onl y and de vices are guaranteed to operate pr operl y onl y within the speci ed rang e . figure 14-1: t ypical i pd vs. v dd (wdt disab led, rc mode) figure 14-2: maxim um i pd vs. v dd (wdt disab led, rc mode) note: the data presented in this section is a statistical summar y of data collected on units from diff erent lots o v er a per iod of time and matr ix samples . 't ypical' represents the mean of the distr ib ution at, 25 c , while 'max' or 'min' represents (mean +3 s ) and (mean -3 s ) respectiv ely where s is standard de viation. 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (v olts) shaded area is be y ond recommended r ange . i pd ( m a) v dd (v olts) 10.000 1.000 0.100 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 85 c 70 c 25 c 0 c -40 c shaded area is be y ond recommended r ange .
pic16c71x ds30272a -page 126 1997 microchip technology inc. applicable devices 710 71 711 715 figure 14-3: t ypical i pd vs. v dd @ 25 c (wdt enab led, rc mode) figure 14-4: maxim um i pd vs. v dd (wdt enab led, rc mode) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (v olts) shaded area is be y ond recommended r ange . 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (v olts) -40 c 0 c 70 c 85 c shaded area is be y ond recommended r ange . figure 14-5: t ypical rc oscillator frequenc y vs. v dd figure 14-6: t ypical rc oscillator frequenc y vs. v dd figure 14-7: t ypical rc oscillator frequenc y vs. v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 fosc(mhz) ce xt = 22 pf , t = 25 c r = 100k r = 10k r = 5k shaded area is be y ond recommended r ange . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 fosc(mhz) ce xt = 100 pf , t = 25 c r = 100k r = 10k r = 5k r = 3.3k shaded area is be y ond recommended r ange . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 1000 900 800 700 600 500 400 300 200 100 0 fosc(khz) ce xt = 300 pf , t = 25 c r = 3.3k r = 5k r = 10k r = 100k shaded area is be y ond recommended r ange .
1997 microchip technology inc. ds30272a -page 127 pic16c71x applicable devices 710 71 711 715 figure 14-8: t ypical i pd vs. v dd br o wn- out detect enab led (rc mode) figure 14-9: maxim um i pd vs. v dd br o wn-out detect enab led (85 c to -40 c, rc mode) this shaded region represents the b uilt-in h ysteresis of the bro wn-out reset circuitr y . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (v olts) i pd ( m a) de vice in bro wn-out de vice no t in bro wn-out reset reset shaded area is be y ond recommended r ange . 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (v olts) i pd ( m a) 4.3 1600 de vice no t in bro wn-out reset de vice in bro wn-out reset this shaded region represents the b uilt-in h ysteresis of the bro wn-out reset circuitr y . shaded area is be y ond recommended r ange . figure 14-10: t ypical i pd vs. timer1 enab led (32 k h z , rc0/rc1 = 33 p f/33 p f , rc mode) figure 14-11: maxim um i pd vs. timer1 enab led (32 k h z , rc0/rc1 = 33 p f/33 p f , 85 c to -40 c, rc mode) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) i pd ( m a) shaded area is be y ond recommended r ange . 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) i pd ( m a) 35 40 45 shaded area is be y ond recommended r ange .
pic16c71x ds30272a -page 128 1997 microchip technology inc. applicable devices 710 71 711 715 figure 14-12: t ypical i dd vs. frequenc y (rc mode @ 22 p f , 25 c) figure 14-13: maxim um i dd vs. frequenc y (rc mode @ 22 p f , -40 c to 85 c) 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 f requency(mhz) i dd ( m a) shaded area is 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v be y ond recommended r ange 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 f requency(mhz) i dd ( m a) shaded area is 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v be y ond recommended r ange
1997 microchip technology inc. ds30272a -page 129 pic16c71x applicable devices 710 71 711 715 figure 14-14: t ypical i dd vs. frequenc y (rc mode @ 100 p f , 25 c) figure 14-15: maxim um i dd vs. frequenc y (rc mode @ 100 p f , -40 c to 85 c) 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 f requency(khz) i dd ( m a) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is be y ond recommended r ange 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 f requency(khz) i dd ( m a) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is be y ond recommended r ange
pic16c71x ds30272a -page 130 1997 microchip technology inc. applicable devices 710 71 711 715 figure 14-16: t ypical i dd vs. frequenc y (rc mode @ 300 p f , 25 c) figure 14-17: maxim um i dd vs. frequenc y (rc mode @ 300 p f , -40 c to 85 c) 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 f requency(khz) i dd ( m a) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 f requency(khz) i dd ( m a) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
1997 microchip technology inc. ds30272a -page 131 pic16c71x applicable devices 710 71 711 715 figure 14-18: t ypical i dd vs . capacitance @ 500 k h z (rc mode) t ab le 14-1: rc oscillator frequencies ce xt re xt a vera g e fosc @ 5v , 25 c 22 pf 5k 4.12 mhz 1.4% 10k 2.35 mhz 1.4% 100k 268 khz 1.1% 100 pf 3.3k 1.80 mhz 1.0% 5k 1.27 mhz 1.0% 10k 688 khz 1.2% 100k 77.2 khz 1.0% 300 pf 3.3k 707 khz 1.4% 5k 501 khz 1.2% 10k 269 khz 1.6% 100k 28.3 khz 1.1% the percentage v ar iation indicated here is par t to par t v ar iation due to nor mal process distr ib ution. the v ar iation indicated is 3 standard de viation from a v er age v alue f or v dd = 5v . capacitance(pf) 600 i dd ( m a) 500 400 300 200 100 0 20 pf 100 pf 300 pf 5.0v 4.0v 3.0v figure 14-19: t ransconductance( gm ) of hs oscillator vs. v dd figure 14-20: t ransconductance( gm ) of lp oscillator vs. v dd figure 14-21: t ransconductance( gm ) of xt oscillator vs. v dd 4.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (v olts) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 max -40 c t yp 25 c min 85 c shaded area is be y ond recommended r ange . 110 100 90 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (v olts) max -40 c t yp 25 c min 85 c shaded area is be y ond recommended r ange . 1000 900 800 700 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) max -40 c t yp 25 c min 85 c v dd (v olts) shaded area is be y ond recommended r ange .
pic16c71x ds30272a -page 132 1997 microchip technology inc. applicable devices 710 71 711 715 figure 14-22: t ypical xt al star tup time vs. v dd (lp mode , 25 c) figure 14-23: t ypical xt al star tup time vs. v dd (hs mode , 25 c) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) star tup time(seconds) 32 khz, 33 pf/33 pf 200 khz, 15 pf/15 pf shaded area is be y ond recommended r ange . 7 6 5 4 3 2 1 4.0 4.5 5.0 5.5 6.0 v dd (v olts) star tup time(ms) 20 mhz, 33 pf/33 pf 8 mhz, 33 pf/33 pf 8 mhz, 15 pf/15 pf 20 mhz, 15 pf/15 pf shaded area is be y ond recommended r ange . figure 14-24: t ypical xt al star tup time vs . v dd (xt mode , 25 c) t ab le 14-2: capacitor selection f or cr ystal oscillator s osc t ype cr ystal freq cap. rang e c1 cap. rang e c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf cr ystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm 70 60 50 40 30 20 10 0 3.0 3.5 2.5 4.0 5.0 5.5 6.0 4.5 v dd (v olts) star tup time(ms) 200 khz, 68 pf/68 pf 200 khz, 47 pf/47 pf 1 mhz, 15 pf/15 pf 4 mhz, 15 pf/15 pf shaded area is be y ond recommended r ange .
1997 microchip technology inc. ds30272a -page 133 pic16c71x applicable devices 710 71 711 715 figure 14-25: t ypical i dd vs. frequenc y (lp mode , 25 c) figure 14-26: maxim um i dd vs. frequenc y (lp mode , 85 c to -40 c) 120 100 80 60 40 20 0 0 50 100 150 200 f requency(khz) i dd ( m a) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 120 100 80 60 40 20 0 0 50 100 150 200 f requency(khz) i dd ( m a) 140 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v figure 14-27: t ypical i dd vs . frequenc y (xt mode , 25 c) figure 14-28: maxim um i dd vs . frequenc y (xt mode , -40 c to 85 c) 1200 1000 800 600 400 200 0 0.0 0.4 f requency(mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0.0 0.4 f requency(mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
pic16c71x ds30272a -page 134 1997 microchip technology inc. applicable devices 710 71 711 715 figure 14-29: t ypical i dd vs . frequenc y (hs mode , 25 c) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 2 4 6 8 10 12 14 16 18 20 f requency(mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v figure 14-30: maxim um i dd vs . frequenc y (hs mode , -40 c to 85 c) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 2 4 6 8 10 12 14 16 18 20 f requency(mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v
1997 microchip technology inc. ds30272a -page 135 pic16c71x applicable devices 710 71 711 715 15.0 e lectrical characteristics f or pic16c71 absolute maxim um ratings ? ambient temper ature under bias ................................................................................................................ . -55 to +125?c stor age temper ature .............................................................................................................................. -65?c to +150?c v oltage on an y pin with respect to v ss (e xcept v dd , m clr , and ra4) .......................................... -0.3v to ( v dd + 0.3v) v oltage on v dd with respect to v ss .......................................................................................................... - 0 .3 to +7.5v v oltage on mclr with respect to v ss (note 2) .................................................................................................. 0 to +14v v oltage on ra4 with respect to vss ................................................................................................................... 0 to +14v t otal po w er dissipation (note 1) ........................................................................................................................... 800 mw maxim um current out of v ss pin ........................................................................................................................... 150 ma maxim um current into v dd pin .............................................................................................................................. 100 ma input clamp current, i ik ( v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maxim um output current sunk b y an y i/o pin .......................................................................................................... 25 ma maxim um output current sourced b y an y i/o pin .................................................................................................... 20 ma maxim um current sunk b y por t a .......................................................................................................................... 80 ma maxim um current sourced b y por t a ..................................................................................................................... 50 ma maxim um current sunk b y por tb ........................................................................................................................ 150 ma maxim um current sourced b y por tb ................................................................................................................... 100 ma note 1: p o w er dissipation is calculated as f ollo ws: pdis = v dd x { i dd - ? i oh } + ? {( v dd - v oh ) x i oh } + ? ( v o l x i ol ) note 2: v oltage spik es belo w v ss at the mclr pin, inducing currents g reater than 80 ma, ma y cause latch-up . thus , a ser ies resistor of 50-100 w should be used when applying a ?o w le v el to the mclr pin r ather than pulling this pin directly to v ss . t ab le 15-1: cr oss ref erence of de vice specs f or oscillator configurations and frequencies of operation (commer cial de vices) ? no tice: stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . osc pic16c71-04 pic16c71-20 pic16lc71-04 jw de vices rc v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ . at 5.5v i pd : 1.0 m a typ . at 4v f req: 4 mhz max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ . at 3.0v i pd : 0.6 m a typ . at 3v f req: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v f req: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v f req: 4 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ . at 5.5v i pd : 1.0 m a typ . at 4v f req: 4 mhz max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ . at 3.0v i pd : 0.6 m a typ . at 3v f req: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v f req: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended f or use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ . at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.0 m a typ . at 4.5v i pd : 1.0 m a typ . at 4.5v i pd : 1.0 m a typ . at 4.5v f req: 4 mhz max. f req: 20 mhz max. f req: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 15 m a typ . at 32 khz, 4.0v i pd : 0.6 m a typ . at 4.0v f req: 200 khz max. not recommended f or u se in lp mode v dd : 3.0v to 6.0v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v f req: 200 khz max. v dd : 3.0v to 6.0v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v f req: 200 khz max. the shaded sections indicate oscillator selections which are tested f or functionality , b ut not f or min/max speci cations . it is recom- mended that the user select the de vice type that ensures the speci cations required.
pic16c71x ds30272a -page 136 1997 microchip technology inc. applicable devices 710 71 711 715 15.1 dc characteristics: pic16c71-04 (commer cial, industrial) pic16c71-20 (commer cial, industrial) dc chara cteristics standar d operating conditions (unless otherwise stated) oper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) p aram no. characteristic sym min t yp? max units conditions d001 d001a supply v oltage v dd 4.0 4.5 - - 6.0 5.5 v v xt , rc and lp osc con gur ation hs osc con gur ation d002* ram data retention v oltage (note 1) v dr - 1.5 - v d003 v dd star t v oltage to ensure inter nal p o w er-on reset signal v por - v ss - v see section on p o w er-on reset f or details d004* v dd r ise r ate to ensure inter nal p o w er-on reset signal s vdd 0.05 - - v/ms see section on p o w er-on reset f or details d010 d013 supply current (note 2) i dd - - 1.8 13.5 3.3 30 ma ma xt , rc osc con gur ation f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con gur ation f osc = 20 mhz, v dd = 5.5v d020 d021 d021a p o w er-do wn current (note 3) i pd - - - 7 1.0 1.0 28 14 16 m a m a m a v dd = 4.0v , wdt enab led, -40 c to +85 c v dd = 4.0v , wdt disab led, -0 c to +70 c v dd = 4.0v , wdt disab led, -40 c to +85 c * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered w ithout losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current consumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er-do wn current in sleep mode does not depend on the oscillator type . p o w er-do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be esti- mated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm.
1997 microchip technology inc. ds30272a -page 137 pic16c71x applicable devices 710 71 711 715 15.2 dc characteristics: pic16lc71-04 (commer cial, industrial) dc chara cteristics standar d operating conditions (unless otherwise stated) ooper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) p aram no. characteristic sym min t yp? max units conditions d001 supply v oltage v dd 3.0 - 6.0 v xt , rc , and lp osc con gur ation d002* ram data retention v oltage (note 1) v dr - 1.5 - v d003 v dd star t v oltage to ensure inter nal p o w er-on reset signal v por - v ss - v see section on p o w er-on reset f or details d004* v dd r ise r ate to ensure inter nal p o w er-on reset signal s vdd 0.05 - - v/ms see section on p o w er-on reset f or details d010 d010a supply current (note 2) i dd - - 1.4 15 2.5 32 ma m a xt , rc osc con gur ation f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con gur ation f osc = 32 khz, v dd = 3.0v , wdt disab led d020 d021 d021a p o w er-do wn current (note 3) i pd - - - 5 0.6 0.6 20 9 12 m a m a m a v dd = 3.0v , wdt enab led, -40 c to +85 c v dd = 3.0v , wdt disab led, 0 c to +70 c v dd = 3.0v , wdt disab led, -40 c to +85 c * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered w ithout losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current consumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er-do wn current in sleep mode does not depend on the oscillator type . p o w er-do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be esti- mated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm.
pic16c71x ds30272a -page 138 1997 microchip technology inc. applicable devices 710 71 711 715 15.3 dc characteristics: pic16c71-04 (commer cial, industrial) pic16c71-20 (commer cial, industrial) pic16lc71-04 (commer cial, industrial) dc chara cteristics standar d operating conditions (unless otherwise stated) ooper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) oper ating v oltage v dd r ange as descr ibed in dc spec section 15.1 and section 15.2 . p aram no. characteristic sym min t yp ? max units conditions input lo w v olta g e i/o por ts v il d030 with ttl b uff er v ss - 0. 1 5 v v f or entire v dd r ange d031 with schmitt t r igger b uff er v ss - 0. 8 v v 4.5 v dd 5.5v d032 mclr , o sc 1 ( in rc mode) v ss - 0.2 v dd v d033 osc1 (in xt , hs and lp) v ss - 0.3 v dd v note1 input high v olta g e i/o por ts (note 4) v ih - d040 with ttl b uff er 2.0 - v dd v 4.5 v dd 5.5v d040a 0. 25 v dd + 0.8v - v dd f or entire v dd r ange d041 with schmitt t r igger b uff er 0.85 v dd - v dd f or entire v dd r ange d042 mcl r , rb0/int 0.85 v dd - v dd v d042a osc1 (xt , hs and lp) 0.7 v dd - v dd v note1 d043 osc1 (in rc mode) 0.9v dd - v dd v d070 por tb w eak pull-up current i purb 50 250 ?400 m a v dd = 5v , v pin = v ss input leaka g e current (notes 2, 3) d060 i/o por ts i il - - 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt , hs and lp osc con gur ation output lo w v olta g e d080 i/o por ts v ol - - 0.6 v i ol = 8.5ma, v dd = 4.5v , -40 c to +85 c d083 osc2/clk out (rc osc con g) - - 0.6 v i ol = 1.6ma, v dd = 4.5v , -40 c to +85 c output high v olta g e d090 i/o por ts (note 3) v oh v dd - 0.7 - - v i oh = -3.0ma, v dd = 4.5v , -40 c to +85 c d092 osc2/clk out (rc osc con g) v dd - 0.7 - - v i oh = -1.3ma, v dd = 4.5v , -40 c to +85 c d130 * open-drain high v olta g e v od - - 14 v ra4 pin ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1 pin is a schmitt tr igger input. it is not recommended that the pic16c71 be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as current sourced b y t he pin. 4: pic16c71 re v . "ax" int pin has a ttl input b uff er . pic16c71 re v . "bx" int pin has a schmitt t r igger input b uff er .
1997 microchip technology inc. ds30272a -page 139 pic16c71x applicable devices 710 71 711 715 capacitive loading specs on output pins d100 osc2 pin c osc2 15 pf in xt , hs and lp modes when e xter nal cloc k is used to dr iv e osc1. d101 all i/o pins and osc2 (in rc mode) c io 50 pf dc chara cteristics standar d operating conditions (unless otherwise stated) ooper ating temper ature 0?c t a +70?c (commercial) -40?c t a +85?c (industr ial) oper ating v oltage v dd r ange as descr ibed in dc spec section 15.1 and section 15.2 . p aram no. characteristic sym min t yp ? max units conditions ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1 pin is a schmitt tr igger input. it is not recommended that the pic16c71 be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as current sourced b y t he pin. 4: pic16c71 re v . "ax" int pin has a ttl input b uff er . pic16c71 re v . "bx" int pin has a schmitt t r igger input b uff er .
pic16c71x ds30272a -page 140 1997 microchip technology inc. applicable devices 710 71 711 715 15.4 timing p arameter symbology the timing par ameter symbols ha v e been created f ollo wing one of the f ollo wing f or mats: figure 15-1: load conditions 1. tpps2pps 2. tpps t f f requency t time lo w ercase letters (pp) and their meanings: pp cc ccp1 osc osc1 c k clk out rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o por t t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-impedance) v v alid l lo w z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf f or all pins e xcept osc2/clk out 15 pf f or osc2 output load condition 1 load condition 2
1997 microchip technology inc. ds30272a -page 141 pic16c71x applicable devices 710 71 711 715 15.5 timing dia grams and speci cations figure 15-2: external cloc k timing t ab le 15-2: external cloc k timing requirements p arameter no. sym characteristic min t yp? max units conditions f os c external clkin frequenc y (note 1) dc 4 mhz xt osc mode dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequenc y (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 1 4 mhz hs osc mode 1 20 mhz hs osc mode 1 t osc external clkin p eriod (note 1) 250 ns xt osc mode 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator p eriod (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 1,000 ns hs osc mode (-04) 50 1,000 ns hs osc mode (-20) 5 m s lp osc mode 2 t cy instruction cyc le time (note 1) 1.0 t cy dc m s t cy = 4/f osc 3 t osl, t osh external cloc k in (osc1) high or lo w time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 t osr, t osf external cloc k in (osc1) rise or f all time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time-base per iod. all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating conditions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current con- sumption. all de vices are tested to oper ate at "min." v alues with an e xter nal cloc k applied to the osc1/clkin pin. when an e xter nal cloc k input is used, the "max." cycle time limit is "dc" (no cloc k) f or all de vices . osc2 is disconnected (has no loading) f or the pic16c71. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clk out
pic16c71x ds30272a -page 142 1997 microchip technology inc. applicable devices 710 71 711 715 figure 15-3: clk out and i/o timing t ab le 15-3: clk out and i/o timing requirements p arameter no. sym characteristic min t yp? max units conditions 10* t osh2c kl osc1 - to clk out 15 30 ns note 1 11* t osh2c kh osc1 - to clk out - 15 30 ns note 1 12* tc kr clk out r ise time 5 15 ns note 1 13* tc kf clk out f all time 5 15 ns note 1 14* tc kl2iov clk out to p or t out v alid 0.5 t cy + 20 ns note 1 15* tiov2c kh p or t in v alid bef ore clk out - 0.25 t cy + 25 ns note 1 16* tc kh2ioi p or t in hold after clk out - 0 ns note 1 17* t osh2iov osc1 - (q1 cycle) to p or t out v alid 80 - 100 ns 18* t osh2ioi osc1 - (q2 cycle) to p or t input in v alid (i/o in hold time) pic16 c 71 100 ns pic16 lc 71 200 ns 19* tiov2osh p or t input v alid to osc1 - (i/o in setup time) 0 ns 20* tior p or t output r ise time pic16 c 71 10 25 ns pic16 lc 71 60 ns 21* tiof p or t output f all time pic16 c 71 10 25 ns pic16 lc 71 60 ns 22??* tinp int pin high or lo w time 20 ns 23??* t rbp rb7:rb4 change int high or lo w time 20 ns * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. ?? these par ameters are asynchronous e v ents not related to an y inter nal cloc k edges . note 1: measurements are tak en in rc mode where clk out output is 4 x t osc . note: ref er to figure 15-1 f or load conditions . osc1 clk out i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old v alue ne w v alue
1997 microchip technology inc. ds30272a -page 143 pic16c71x applicable devices 710 71 711 715 figure 15-4: reset, w atc hdog time r , oscillator star t-up timer and p o wer -up timer timing t ab le 15-4: reset, w atc hdog timer , oscillator star t-up timer and p o wer -up timer requirements p arameter no. sym characteristic min t yp? max units conditions 30 tmcl mclr pulse width (lo w) 200 ns v dd = 5v , -40?c to +85?c 31 t wdt w atchdog timer time-out p er iod 7* 18 33* ms v dd = 5v , -40?c to +85?c (no prescaler) 32 t ost oscillation star t-up timer p er iod 1024 t osc t osc = osc1 per iod 33 tpwr t p o w er-up timer p er iod 28* 72 132* ms v dd = 5v , -40?c to +85?c 34 t ioz i/o high impedance from mclr lo w 100 ns * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. v dd mclr inter nal por pwr t time-out osc time-out inter nal reset w atchdog timer reset 33 32 30 31 34 i/o pins 34 note: ref er to figure 15-1 f or load conditions .
pic16c71x ds30272a -page 144 1997 microchip technology inc. applicable devices 710 71 711 715 figure 15-5: timer0 external cloc k t imings t ab le 15-5: timer0 external cloc k requirements p aram no. sym characteristic min t yp? max units conditions 40 * tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ns must also meet par ameter 42 with prescaler 10 ns 41 * tt0l t0cki lo w pulse width no prescaler 0.5 t cy + 20 ns must also meet par ameter 42 with prescaler 10 ns 42 * tt0p t0cki p er iod no prescaler t cy + 40 ns n = prescale v alue (2, 4,..., 256) with prescaler greater of: 20 ns or t cy + 40 n * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note: ref er to figure 15-1 f or load conditions . 41 42 40 ra4/t0cki tmr0
1997 microchip technology inc. ds30272a -page 145 pic16c71x applicable devices 710 71 711 715 t ab le 15-6: a/d con ver ter characteristics p aram no. sym characteristic min t yp? max units conditions a01 n r resolution 8 bits bits v ref = v dd = 5.12v, v ss v ai n v ref a02 e abs absolute e rror pic16 c 71 < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref pic16 lc 71 < 2 lsb v ref = v dd = 3.0v (note 3) a03 e il integ r al linear ity error pic16 c 71 < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref pic16 lc 71 < 2 lsb v ref = v dd = 3.0v (note 3) a04 e dl diff erential linear ity error pic16 c 71 < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref pic16 lc 71 < 2 lsb v ref = v dd = 3.0v (note 3) a05 e f s full scale error pic16 c 71 < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref pic16 lc 71 < 2 lsb v ref = v dd = 3.0v (note 3) a06 e o ff offset error pic16 c 71 < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref pic16 lc 71 < 2 lsb v ref = v dd = 3.0v (note 3) a10 monotonicity guar anteed v ss v ain v ref a20 v ref ref erence v oltage 3.0v v dd + 0.3 v a25 v ain analog input v oltage v ss - 0.3 v ref v a30 z ain recommended impedance of analog v oltage source 10.0 k w a40 i ad a/d con v ersion current ( v dd ) 180 m a a v er age current consump- tion whe n a /d is on. (note 1) a50 i ref v ref input current (note 2) pic16 c 71 10 1 000 4 0 m a m a dur ing v ain acquisition. based on diff erential of v hold to v ain . t o charge c hold see section 7.1 . dur ing a/d con v ersion cycle pic16 lc 71 1 10 ma m a dur ing v ain acquisition. based on diff erential of v hold to v ain . t o charge c hold see section 7.1 . dur ing a/d con v ersion cycle * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: when a/d is off , it will not consume an y current other than minor leakage current. the po w er-do wn current spec includes an y such leakage from the a/d module . 2: v ref current is from ra3 pin or v dd pin, whiche v er is selected as ref erence input. 3: these speci cations apply if v ref = 3.0v and if v dd 3 3.0v . v a in m ust be betw een v ss and v ref .
pic16c71x ds30272a -page 146 1997 microchip technology inc. applicable devices 710 71 711 715 figure 15-6: a /d con v er sion timing t ab le 15-7: a/d con ver sion requirements p aram no. sym characteristic min t yp? max units conditions 130 t ad a/d cloc k per iod pic16 c 71 2.0 m s t osc based, v ref 3 3.0v pic16 lc 71 2.0 m s t osc based, v ref full r ange pic16 c 71 2.0 4.0 6.0 m s a/d rc mode pic16 lc 71 3.0 6.0 9.0 m s a/d rc mode 131 t cnv con v ersion time (not including s/h time) (note 1) 9.5 t ad 132 t acq acquisition time note 2 5* 20 m s m s the minim um time is the ampli- er settling time . this ma y be used if the "ne w" input v oltage has not changed b y more than 1 lsb (i.e ., 19.5 mv @ 5.12v) from the last sampled v oltage (as stated on c hold ). 134 t go q4 to a/d cloc k star t t osc/2 if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 135 t swc switching from con v er t ? sample time 1.5 t ad * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. these speci cations ensured b y design. note 1: adres register ma y be read on the f ollo wing t cy cycle . 2: see section 7.1 f or min conditions . 131 130 132 bsf adcon 0 , go q4 a/d clk a/d d a t a adres adif go sample old_d a t a sampling st opped done new_d a t a (t osc /2) (1) 7 6 5 4 3 2 1 0 note 1: if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 1 tcy
1997 microchip technology inc. ds30272a -page 147 pic16c71x applicable devices 710 71 711 715 16.0 dc and a c characteristics graphs and t ab les f or pic16c71 the g r aphs and tab les pro vided in this section are f or design guidance and are not tested or guar anteed. in some graphs or tab les the data presented are out- side speci ed operating rang e (e .g. outside speci- ed v dd rang e). this is f or inf ormation onl y and de vices are guaranteed to operate pr operl y onl y within the speci ed rang e . figure 16-1: t ypical rc oscillator frequenc y vs. t emperature note: the data presented in this section is a sta- tistical summar y of data collected on units from diff erent lots o v er a per iod of time and matr ix samples . 't ypical' represents the mean of the distr ib ution while 'max' or 'min' represents (mean + 3 s ) and (mean - 3 s ) respectiv ely where s is standard de viation. f requency nor maliz ed to 25 c 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 f osc f osc ( 25 c) t( c) re xt = 10k ce xt = 100 pf v dd = 5.5v v dd = 3.5v 0 10 20 30 40 50 60 70 figure 16-2: t ypical rc oscillator frequenc y vs. v dd figure 16-3: t ypical rc oscillator frequenc y vs. v dd 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) f osc (mhz) r = 4.7k r = 10k r = 100k ce xt = 20 pf , t = 25 c 2.0 1.8 1.0 0.8 0.6 0.4 0.2 0.0 3.0 4.0 3.5 4.5 5.0 5.5 6.0 v dd (v olts) f osc (mhz) r = 3.3k r = 4.7k r = 10k ce xt = 100 pf , t = 25 c r = 100k 1.6 1.4 1.2
pic16c71x ds30272a -page 148 1997 microchip technology inc. applicable devices 710 71 711 715 figure 16-4: t ypical rc oscillator frequenc y vs. v dd figure 16-5: t ypical i pd vs. v dd w atc hdog timer disab led 25 c 0 3.0 v dd (v olts) f osc (mhz) ce xt = 300 pf , t = 25 c r = 100k 3.5 4.0 4.5 5.0 5.5 6.0 .1 .2 .3 .4 .5 .6 .7 .8 r = 10k r = 4.7k r = 3.3k 0.0 3.0 v dd (v olts) i pd ( m a) 0.1 0.2 0.3 0.4 0.5 0.6 3.5 4.0 4.5 5.0 5.5 6.0 t ab le 16-1: rc oscillator frequencies the percentage v ar iation indicated here is par t to par t v ar iation due to nor mal process distr ib ution. the v ar ia- tion indicated is 3 standard de viation from a v er age v alue f or v dd = 5v . figure 16-6: t ypical i pd vs. v dd w atc hdog timer enab led 25 c ce xt re xt a vera g e f osc @ 5v , 25 c 20 p f 4.7k 10k 100k 4.52 mhz 2.47 mhz 290.86 khz 17.35% 10.10% 11.90% 100 p f 3.3k 4.7k 10k 100k 1.92 mhz 1.49 mhz 788.77 khz 88.11 khz 9.43% 9.83% 10.92% 16.03% 300 p f 3.3k 4.7k 10k 100k 726.89 khz 573.95 khz 307.31 khz 33.82 khz 10.97% 10.14% 10.43% 11.24% v dd (v olts) i pd ( m a) 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 4 6 8 10 12 14 data based on matr ix samples . see rst page of this section f or details .
1997 microchip technology inc. ds30272a -page 149 pic16c71x applicable devices 710 71 711 715 figure 16-7: maxim um i pd vs. v dd w atc hdog disab led 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) 0 c -55 c -40 c 70 c 85 c 125 c i pd ( m a) 25 20 15 10 5 0 figure 16-8: maxim um i pd vs. v dd w atc hdog enab led i pd , with w atchdog timer enab led, has tw o components: the leakage current which increases with higher temper a- ture and the oper ating current of the w atchdog timer logic which increases with lo w er temper ature . at -40 c , the latter dominates e xplaining the apparently anomalous beha vior . 0 c -55 c -40 c 70 c 85 c 125 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) i pd ( m a) 45 40 35 30 25 20 15 10 5 0 figure 16-9: v th (input threshold v olta g e) of i/o pins vs. v dd v dd (volts) 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 25?c, typ min (-40?c to 85?c) 0.60 max (-40?c to 85?c) v th (volts) data based on matr ix samples . see rst page of this section f or details .
pic16c71x ds30272a -page 150 1997 microchip technology inc. applicable devices 710 71 711 715 figure 16-10: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd figure 16-11: v th (input threshold v olta g e) of osc1 input (in xt , hs, and lp modes) vs. v dd 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) note: these input pins ha v e a schmitt t r igger input b uff er . v ih , v il (v olts) v ih , max (-40 c to 85 c) v ih , t yp (25 c) v ih , min (-40 c to 85 c) v il , max (-40 c to 85 c) v il , t yp (25 c) v il , min (-40 c to 85 c) 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (v olts) v th (v olts) m in (-40 c to 85 c) m ax (-40 c to 85 c) m in (-40 c to 85 c) t yp (25 c) data based on matr ix samples . see rst page of this section f or details .
1997 microchip technology inc. ds30272a -page 151 pic16c71x applicable devices 710 71 711 715 figure 16-12: t ypical i dd vs. freq (ext cloc k, 25 c) figure 16-13: maxim um, i dd vs. freq (ext cloc k, -40 to +85 c) 1 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) f requency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) f requency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 data based on matr ix samples . see rst page of this section f or details .
pic16c71x ds30272a -page 152 1997 microchip technology inc. applicable devices 710 71 711 715 figure 16-14: maxim um i d d vs. freq with a/d off (ext cloc k, -55 to +125 c) 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) f requency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 figure 16-15: wdt timer time-out p eriod vs. v d d 50 45 40 35 30 25 20 15 10 5 2 3 4 5 6 7 v dd (v olts) wdt p er iod (ms) max, 85 c max, 70 c t yp , 25 c min, 0 c min, -40 c figure 16-16: t ransconductance ( gm ) of hs oscillator vs. v dd min, 85 c t yp , 25 c max, -40 c 2 3 4 5 6 7 v dd (v olts) gm ( m a/v) 0 9000 8000 7000 6000 5000 4000 3000 2000 1000 data based on matr ix samples . see rst page of this section f or details .
1997 microchip technology inc. ds30272a -page 153 pic16c71x applicable devices 710 71 711 715 figure 16-17: t ransconductance ( gm ) of lp oscillator vs. v dd figure 16-18: t ransconductance ( gm ) of xt oscillator vs. v dd min, 85 c t yp , 25 c max, -40 c 225 200 175 150 125 100 75 50 25 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v olts) gm ( m a/v) min, 85 c t yp , 25 c max, -40 c 2 3 4 5 6 7 v dd (v olts) 2500 2000 1500 1000 500 0 gm ( m a/v) figure 16-19: i oh vs. v oh , v dd = 3v figure 16-20: i oh vs. v oh , v dd = 5v min, 85 c t yp , 25 c max, -40 c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v oh (v olts) i oh (ma) 0 -5 -10 -15 -20 -25 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0 .0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v oh (v olts) i oh (ma) min @ 85 c t yp @ 25 c max @ -40 c data based on matr ix samples . see rst page of this section f or details .
pic16c71x ds30272a -page 154 1997 microchip technology inc. applicable devices 710 71 711 715 figure 16-21: i ol vs. v ol , v dd = 3v 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ol (v olts ) i ol ( m a) m ax @ -40 c t yp @ 25 c m in @ +85 c figure 16-22: i ol vs. v ol , v dd = 5v m ax @ -40 c 80 90 70 60 50 40 30 20 10 0 v ol (v olts ) i ol ( m a) m in @ +85 c t yp @ 25 c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 data based on matr ix samples . see rst page of this section f or details .
1997 microchip technology inc. ds30272a -page 155 pic16c71x 17.0 p ac ka ging inf ormation 17.1 18-lead cer amic cerdip dual in-line with windo w (300 mil) (jw) p ac ka g e gr oup: ceramic cerdip dual in-line (cdp) symbol millimeter s inc hes min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.381 1.7780 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 t ypical 0.050 0.065 t ypical c 0.203 0.381 t ypical 0.008 0.015 t ypical d 22.352 23.622 0.880 0.930 d1 20.320 20.320 ref erence 0.800 0.800 ref erence e 7.620 8.382 0.300 0.330 e1 5.588 7.874 0.220 0.310 e1 2.540 2.540 ref erence 0.100 0.100 ref erence ea 7.366 8.128 t ypical 0.290 0.320 t ypical eb 7.620 10.160 0.300 0.400 l 3.175 3.810 0.125 0.150 n 18 18 18 18 s 0.508 1.397 0.020 0.055 s1 0.381 1.270 0.015 0.050 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a l a c e a e b e1 a2
pic16c71x ds30272a -page 156 1997 microchip technology inc. 17.2 18-lead plastic dual in-line (300 mil) (p) p ac ka g e gr oup: plastic dual in-line (pla) symbol millimeter s inc hes min max notes min max notes a 0 10 0 10 a 4.064 0.160 a1 0.381 0.015 a2 3.048 3.810 0.120 0.150 b 0.355 0.559 0.014 0.022 b1 1.524 1.524 ref erence 0.060 0.060 ref erence c 0.203 0.381 t ypical 0.008 0.015 t ypical d 22.479 23.495 0.885 0.925 d1 20.320 20.320 ref erence 0.800 0.800 ref erence e 7.620 8.255 0.300 0.325 e1 6.096 7.112 0.240 0.280 e1 2.489 2.591 t ypical 0.098 0.102 t ypical ea 7.620 7.620 ref erence 0.300 0.300 ref erence eb 7.874 9.906 0.310 0.390 l 3.048 3.556 0.120 0.140 n 18 18 18 18 s 0.889 0.035 s1 0.127 0.005 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
1997 microchip technology inc. ds30272a -page 157 pic16c71x 17.3 18-lead plastic surface m ount (soic - wide , 300 mil bod y) (so) p ac ka g e gr oup: plastic soic (so) symbol millimeter s inc hes min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 11.353 11.735 0.447 0.462 e 7.416 7.595 0.292 0.299 e 1.270 1.270 ref erence 0.050 0.050 ref erence h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 n 18 18 18 18 cp 0.102 0.004 b e n inde x area chamf er h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
pic16c71x ds30272a -page 158 1997 microchip technology inc. 17.4 20-lead plastic surfa ce mount (ssop - 209 mil bod y 5.30 mm) (ss) note 1: dimensions d1 and e1 do not include mold protr usion. allo w ab le mold protr usion is 0.25m/m (0.010? per side . d1 and e1 dimensions including mold mismatch. 2: dimension ? does not include dambar protr usion, allo w ab le dambar protr usion shall be 0.08m/m (0.003?max. 3: this outline conf or ms to jedec ms-026. p ac ka g e gr oup: plastic ssop symbol millimeter s inc hes min max notes min max notes a 0 8 0 8 a 1.730 1.990 0.068 0.078 a1 0.050 0.210 0.002 0.008 b 0.250 0.380 0.010 0.015 c 0.130 0.220 0.005 0.009 d 7.070 7.330 0.278 0.289 e 5.200 5.380 0.205 0.212 e 0.650 0.650 ref erence 0.026 0.026 ref erence h 7.650 7.900 0.301 0.311 l 0.550 0.950 0.022 0.037 n 20 20 20 20 cp - 0.102 - 0.004 inde x area n h 1 2 3 e e b cp d a a1 base plane seating plane l c a
1997 microchip technology inc. ds30272a -page 159 pic16c71x 17.5 p ac ka g e marking inf ormation legend: mm...m xx...x aa bb c d 1 e microchip par t n umber inf or mation customer speci c inf or mation* y ear code (last 2 digits of calender y ear) w eek code (w eek of j an uar y 1 is w eek '01? f acility code of the plant at which w af er is man uf actured. c = chandler , ar iz ona, u .s .a. mask re vision n umber f or microcontroller assemb ly code of the plant or countr y of or igin in which par t w as assemb led. in the e v ent the full microchip par t n umber cannot be mar k ed on one line , it will be carr ied o v er to the ne xt line thus limiting the n umber of a v ailab le char acters f or customer speci c inf or mation. note : standard o tp mar king consists of microchip par t n umber , y ear code , w eek code , f acility code , mask re vision n umber , and assemb ly code . f or o tp mar king be y ond this , cer tain pr ice adders apply . please chec k with y our microchip sales of ce . f or qtp de vices , an y special mar king adders are included in qtp pr ice . * mmmmmmmmmmmmm xxxxxxxxx xxxxxxx aabbcde 18-lead pdip 18-lead soic xxxxxxx xxxxx aabbcde xxxxxxx xxxxx mmmmmmmmmm mmmmmm xxxxxxxx aabbcde 18-lead cerdip windo w ed pic16c711-04/p 9452cba example example -20/50 9447cba pic16c715 pic16c71 /jw 945/cbt example s = t empe , ar iz ona, u .s .a. aabbcae xxxxxxxx xxxxxxxx 20-lead ssop 9517sbp 20i/ss025 pic16c710 example
pic16c71x ds30272a -page 160 1997 microchip technology inc. no tes:
1997 microchip technology inc. ds30272a -page 161 pic16c71x appendix a: the f ollo wing are the list of modi cations o v er the pic16c5x microcontroller f amily: 1. instr uction w ord length is increased to 14-bits . this allo ws larger page siz es both in prog r am memor y (1k no w as opposed to 512 bef ore) and register le (68 b ytes no w v ersus 32 b ytes bef ore). 2. a pc high latch register (pcla th) is added to handle prog r am memor y paging. bits p a2, p a1, p a0 are remo v ed from st a tus register . 3. data memor y paging is rede ned slightly . s t a tus register is modi ed. 4. f our ne w instr uctions ha v e been added: return, retfie, addlw , and sublw . t w o instr uctions tris and option are being phased out although the y are k ept f or compati- bility with pic16c5x. 5. option and tris registers are made address- ab le . 6. interr upt capability is added. interr upt v ector is at 0004h. 7. stac k siz e is increased to 8 deep . 8. reset v ector is changed to 0000h. 9. reset of all registers is re visited. fiv e diff erent reset (and w ak e-up) types are recogniz ed. reg- isters are reset diff erently . 10. w ak e up from sleep through interr upt is added. 11. t w o separ ate timers , oscillator star t-up timer (ost) and p o w er-up timer (pwr t) are included f or more reliab le po w er-up . these tim- ers are in v ok ed selectiv ely to a v oid unneces- sar y dela ys on po w er-up and w ak e-up . 12. por tb has w eak pull-ups and interr upt on change f eature . 13. t0cki pin is also a por t pin (ra4) no w . 14. fsr is made a full eight bit register . 15. ?n-circuit ser ial prog r amming is made possib le . the user can prog r am pic16cxx de vices using only v e pins: v dd , v ss , mclr /v pp , rb6 (cloc k) and rb7 (data in/out). 16. pcon status register is added with a p o w er-on reset status bit ( por ). 17. code protection scheme is enhanced such that por tions of the prog r am memor y can be pro- tected, while the remainder is unprotected. 18. bro wn-out protection circuitr y has been added. controlled b y con gur ation w ord bit boden. bro wn-out reset ensures the de vice is placed in a reset condition if v dd dips belo w a x ed set- point. appendix b: compatibility t o con v er t code wr itten f or pic16c5x to pic16cxx, the user should tak e the f ollo wing steps: 1. remo v e an y prog r am memor y page select oper ations (p a2, p a1, p a0 bits) f or call , goto . 2. re visit an y computed jump oper ations (wr ite to pc or add to pc , etc.) to mak e sure page bits are set proper ly under the ne w scheme . 3. eliminate an y data memor y page s witching. rede ne data v ar iab les to reallocate them. 4. v er ify all wr ites to st a tus , option, and fsr registers since these ha v e changed. 5. change reset v ector to 0000h.
pic16c71x ds30272a -page 162 1997 microchip technology inc. appendix c: what s ne w 1. consolidated all pin compatib le 18-pin a/d based de vices into one data sheet. appendix d: what s chang ed 1. minor changes , spelling and g r ammatical changes . 2. lo w v oltage oper ation on the pic16lc710/711/ 715 has been reduced from 3.0v to 2.5v . 3. p ar t n umbers of the pic16c70 and pic16c71a ha v e changed to pic16c710 and pic16c711, respectiv ely .
1997 microchip technology inc. ds30390d -page 163 pic16c71x inde x a a/d accuracy/error ........................................................... 44 adif bit ...................................................................... 39 analog input model block diagram ............................ 40 analog-to-digital converter ........................................ 37 configuring analog port pins ..................................... 41 configuring the interrupt ............................................ 39 configuring the module .............................................. 39 connection considerations ........................................ 44 conversion clock ....................................................... 41 conversion time ........................................................ 43 conversions ............................................................... 42 converter characteristics .......................... 99, 122, 145 delays ........................................................................ 40 effects of a reset ....................................................... 44 equations ................................................................... 40 faster conversion - lower resolution trade-off ....... 43 flowchart of a/d operation ........................................ 45 go/ done bit ............................................................. 39 internal sampling switch (rss) impedence ............... 40 minimum charging time ............................................ 40 operation during sleep ............................................. 44 sampling requirements ............................................. 40 source impedence ..................................................... 40 time delays ............................................................... 40 transfer function ....................................................... 45 absolute maximum ratings ............................... 89, 111, 135 ac characteristics pic16c710 .............................................................. 101 pic16c711 .............................................................. 101 pic16c715 .............................................................. 125 adcon0 register .............................................................. 37 adcon1 ............................................................................ 37 adcon1 register ........................................................ 14, 37 adcs0 bit .......................................................................... 37 adcs1 bit .......................................................................... 37 adie bit ........................................................................ 19, 20 adif bit ........................................................................ 21, 37 adon bit ............................................................................ 37 adres register .................................................... 15, 37, 39 alu ...................................................................................... 7 application notes an546 ........................................................................ 37 an552 ........................................................................ 27 an556 ........................................................................ 23 an607, power-up trouble shooting .......................... 53 architecture harvard ........................................................................ 7 overview ...................................................................... 7 von neumann ............................................................... 7 assembler mpasm assembler .................................................... 86 b block diagrams analog input model .................................................... 40 on-chip reset circuit ................................................ 52 pic16c71x .................................................................. 8 ra3/ra0 port pins .................................................... 25 ra4/t0cki pin ........................................................... 25 rb3:rb0 port pins .................................................... 27 rb7:rb4 pins ............................................................ 28 rb7:rb4 port pins ..................................................... 28 timer0 ........................................................................ 31 timer0/wdt prescaler ............................................... 34 watchdog timer ......................................................... 65 boden bit .......................................................................... 48 bor bit ........................................................................ 22, 54 brown-out reset (bor) ...................................................... 53 c c bit .................................................................................... 17 c16c71 .............................................................................. 47 carry bit ................................................................................ 7 chs0 bit ............................................................................. 37 chs1 bit ............................................................................. 37 clocking scheme ................................................................ 10 code examples call of a subroutine in page 1 from page 0 ............... 24 changing prescaler (timer0 to wdt) ........................ 35 changing prescaler (wdt to timer0) ........................ 35 doing an a/d conversion ........................................... 42 i/o programming ........................................................ 30 indirect addressing ..................................................... 24 initializing porta ...................................................... 25 initializing portb ...................................................... 27 saving status and w registers in ram ................. 64 code protection ........................................................... 47, 67 computed goto ............................................................... 23 configuration bits ............................................................... 47 cp0 bit ......................................................................... 47, 48 cp1 bit ................................................................................ 48 d dc bit .................................................................................. 17 dc characteristics ........................................................... 147 pic16c71 ................................................................ 136 pic16c710 ........................................................ 90, 101 pic16c711 ........................................................ 90, 101 pic16c715 ...................................................... 113, 125 development support .................................................... 3, 85 development tools ............................................................. 85 diagrams - see block diagrams digit carry bit ........................................................................ 7 direct addressing ............................................................... 24 e electrical characteristics pic16c71 ................................................................ 135 pic16c710 ................................................................. 89 pic16c711 ................................................................. 89 pic16c715 .............................................................. 111 external brown-out protection circuit ................................. 60 external power-on reset circuit ........................................ 60 f family of devices pic16c71x ................................................................... 4 fosc0 bit .................................................................... 47, 48 fosc1 bit .................................................................... 47, 48 fsr register ......................................................... 15, 16, 24 fuzzy logic dev. system ( fuzzy tech -mp) ..................... 87 g general description .............................................................. 3 gie bit .......................................................................... 19, 61 go/ done bit ...................................................................... 37
pic16c71x ds30390d -page 164 1997 microchip technology inc. i i/o ports porta ....................................................................... 25 portb ....................................................................... 27 section ....................................................................... 25 i/o programming considerations ....................................... 30 icepic low-cost pic16cxxx in-circuit emulator ........... 85 in-circuit serial programming ...................................... 47, 67 indf register ........................................................ 14, 16, 24 indirect addressing ............................................................ 24 instruction cycle ................................................................. 10 instruction flow/pipelining ................................................. 10 instruction format .............................................................. 69 instruction set addlw ...................................................................... 71 addwf ...................................................................... 71 andlw ...................................................................... 71 andwf ...................................................................... 71 bcf ............................................................................ 72 bsf ............................................................................ 72 btfsc ....................................................................... 72 btfss ....................................................................... 73 call .......................................................................... 73 clrf .......................................................................... 74 clrw ........................................................................ 74 clrwdt .................................................................... 74 comf ........................................................................ 75 decf ......................................................................... 75 decfsz ..................................................................... 75 goto ........................................................................ 76 incf ........................................................................... 76 incfsz ...................................................................... 77 iorlw ....................................................................... 77 iorwf ....................................................................... 78 movf ......................................................................... 78 movlw ..................................................................... 78 movwf ..................................................................... 78 nop ........................................................................... 79 option ..................................................................... 79 retfie ...................................................................... 79 retlw ...................................................................... 80 return .................................................................... 80 rlf ............................................................................ 81 rrf ............................................................................ 81 sleep ....................................................................... 82 sublw ...................................................................... 82 subwf ...................................................................... 83 swapf ...................................................................... 83 tris ........................................................................... 83 xorlw ...................................................................... 84 xorwf ...................................................................... 84 section ....................................................................... 69 summary table .......................................................... 70 int interrupt ....................................................................... 63 intcon register ............................................................... 19 inte bit .............................................................................. 19 intedg bit ................................................................... 18, 63 internal sampling switch (rss) impedence ....................... 40 interrupts ............................................................................ 47 a/d ............................................................................. 61 external ...................................................................... 61 portb change ......................................................... 61 portb change ............................................................ 63 rb7:rb4 port change ............................................... 27 section ....................................................................... 61 tmr0 ......................................................................... 63 tmr0 overflow .......................................................... 61 intf bit .............................................................................. 19 irp bit ................................................................................ 17 k keeloq evaluation and programming tools ................... 87 l loading of pc .................................................................... 23 lp ...................................................................................... 54 m mclr ........................................................................... 52, 56 memory data memory ............................................................. 12 program memory ....................................................... 11 register file maps pic16c71 .......................................................... 12 pic16c710 ........................................................ 12 pic16c711 ........................................................ 13 pic16c715 ........................................................ 13 mp-driveway ? - application code generator .................. 87 mpeen bit ................................................................... 22, 48 mplab ? c ........................................................................ 87 mplab ? integrated development environment software ............................................................................. 86 o opcode ........................................................................... 69 option register ............................................................... 18 orthogonal ........................................................................... 7 osc selection .................................................................... 47 oscillator hs ........................................................................ 49, 54 lp ........................................................................ 49, 54 rc ............................................................................. 49 xt ........................................................................ 49, 54 oscillator configurations .................................................... 49 oscillator start-up timer (ost) ......................................... 53 p packaging 18-lead cerdip w/window ................................... 155 18-lead pdip .......................................................... 156 18-lead soic .......................................................... 157 20-lead ssop ........................................................ 158 paging, program memory .................................................. 23 pcl register ................................................... 14, 15, 16, 23 pclath ....................................................................... 57, 58 pclath register ............................................ 14, 15, 16, 23 pcon register ............................................................ 22, 54 pd bit ..................................................................... 17, 52, 55 per bit ............................................................................... 22 pic16c71 ........................................................................ 147 ac characteristics ................................................... 147 picdem-1 low-cost pic16/17 demo board .................... 86 picdem-2 low-cost pic16cxx demo board .................. 86 picdem-3 low-cost pic16cxxx demo board ............... 86 picmaster in-circuit emulator ..................................... 85 picstart plus entry level development system ......... 85 pie1 register ..................................................................... 20 pin functions mclr / v pp ................................................................... 9 osc1/clkin ............................................................... 9 osc2/clkout ........................................................... 9 ra0/an0 ...................................................................... 9 ra1/an1 ...................................................................... 9
1997 microchip technology inc. ds30390d -page 165 pic16c71x ra2/an2 ...................................................................... 9 ra3/an3/ v ref ............................................................. 9 ra4/t0cki ................................................................... 9 rb0/int ....................................................................... 9 rb1 .............................................................................. 9 rb2 .............................................................................. 9 rb3 .............................................................................. 9 rb4 .............................................................................. 9 rb5 .............................................................................. 9 rb6 .............................................................................. 9 rb7 .............................................................................. 9 v dd .............................................................................. 9 v ss ............................................................................... 9 pinout descriptions pic16c71 .................................................................... 9 pic16c710 .................................................................. 9 pic16c711 .................................................................. 9 pic16c715 .................................................................. 9 pir1 register ..................................................................... 21 pop ................................................................................... 23 por ............................................................................. 53, 54 oscillator start-up timer (ost) ........................... 47, 53 power control register (pcon) ................................ 54 power-on reset (por) ............................ 47, 53, 57, 58 power-up timer (pwrt) ..................................... 47, 53 time-out sequence .................................................... 54 time-out sequence on power-up .............................. 59 to ........................................................................ 52, 55 por bit ........................................................................ 22, 54 port rb interrupt ................................................................ 63 porta ......................................................................... 57, 58 porta register .................................................... 14, 15, 25 portb ......................................................................... 57, 58 portb register .................................................... 14, 15, 27 power-down mode (sleep) .............................................. 66 prescaler, switching between timer0 and wdt ............... 35 pro mate ii universal programmer .............................. 85 program branches ............................................................... 7 program memory paging ........................................................................ 23 program memory maps pic16c71 .................................................................. 11 pic16c710 ................................................................ 11 pic16c711 ................................................................ 11 pic16c715 ................................................................ 11 program verification .......................................................... 67 ps0 bit ............................................................................... 18 ps1 bit ............................................................................... 18 ps2 bit ............................................................................... 18 psa bit ............................................................................... 18 push ................................................................................. 23 pwrt power-up timer (pwrt) ........................................... 53 pwrte bit ................................................................... 47, 48 r rbie bit .............................................................................. 19 rbif bit .................................................................. 19, 27, 63 rbpu bit ............................................................................ 18 rc ...................................................................................... 54 rc oscillator ................................................................ 51, 54 read-modify-write ............................................................. 30 register file ....................................................................... 12 registers maps pic16c71 .......................................................... 12 pic16c710 ........................................................ 12 pic16c711 ......................................................... 13 pic16c715 ......................................................... 13 reset conditions ........................................................ 56 summary ............................................................. 14?? reset ........................................................................... 47, 52 reset conditions for special registers .............................. 56 rp0 bit ......................................................................... 12, 17 rp1 bit ................................................................................ 17 s seeval evaluation and programming system ............... 87 services one-time-programmable (otp) devices .................... 5 quick-turnaround-production (qtp) devices .............. 5 serialized quick-turnaround production (sqtp) devices ......................................................................... 5 sleep ......................................................................... 47, 52 software simulator (mplab ? sim) ................................... 87 special features of the cpu .............................................. 47 special function registers pic16c71 ................................................................... 14 pic16c710 ................................................................. 14 pic16c711 ................................................................. 14 special function registers, section ................................... 14 stack ................................................................................... 23 overflows .................................................................... 23 underflow ................................................................... 23 status register ............................................................... 17 t t0cs bit .............................................................................. 18 t0ie bit ............................................................................... 19 t0if bit ............................................................................... 19 t ad ..................................................................................... 41 timer0 rtcc ................................................................... 57, 58 timers timer0 block diagram .................................................... 31 external clock .................................................... 33 external clock timing ........................................ 33 increment delay ................................................. 33 interrupt .............................................................. 31 interrupt timing .................................................. 32 prescaler ............................................................ 34 prescaler block diagram .................................... 34 section ............................................................... 31 switching prescaler assignment ........................ 35 synchronization .................................................. 33 t0cki ................................................................. 33 t0if .................................................................... 63 timing ................................................................. 31 tmr0 interrupt ................................................... 63 timing diagrams a/d conversion ....................................... 100, 124, 146 brown-out reset .................................................. 53, 97 clkout and i/o ....................................... 96, 119, 142 external clock timing ................................ 95, 118, 141 power-up timer ................................................. 97, 143 reset ................................................................. 97, 143 start-up timer .................................................... 97, 143 time-out sequence .................................................... 59 timer0 ................................................. 31, 98, 121, 144 timer0 interrupt timing .............................................. 32 timer0 with external clock ......................................... 33 wake-up from sleep through interrupt ..................... 67 watchdog timer ................................................ 97, 143
pic16c71x ds30390d -page 166 1997 microchip technology inc. to bit ................................................................................. 17 tose bit ............................................................................. 18 trisa register ...................................................... 14, 16, 25 trisb register ...................................................... 14, 16, 27 two? complement .............................................................. 7 u upward compatibility ........................................................... 3 uv erasable devices ........................................................... 5 w w register alu .............................................................................. 7 wake-up from sleep ........................................................ 66 watchdog timer (wdt) ................................... 47, 52, 56, 65 wdt ................................................................................... 56 block diagram ............................................................ 65 programming considerations .................................... 65 timeout ................................................................ 57, 58 wdt period ........................................................................ 65 wdte bit ...................................................................... 47, 48 z z bit .................................................................................... 17 zero bit ................................................................................. 7 list of examples example 3-1: instruction pipeline flow ........................... 10 example 4-1: call of a subroutine in page 1 from page 0 ...................................................... 24 example 4-2: indirect addressing ................................... 24 example 5-1: initializing porta ..................................... 25 example 5-2: initializing portb ..................................... 27 example 5-3: read-modify-write instructions on an i/o port ........................................... 30 example 6-1: c hanging prescaler (timer0 ? wdt) ........ 35 example 6-2: changing prescaler (wdt ? timer0) ........ 35 equation 7-1: a/d minimum charging time .................... 40 example 7-1: calculating the minimum required aquisition t ime ......................................... 40 example 7-2: a /d conversion ......................................... 42 example 7-3: 4-bit vs . 8-bit conversion times ............... 43 example 8-1: saving status and w registers in ram ...................................................... 64 list of figures figure 3-1: pic16c71x block diagram ........................ 8 figure 3-2: clock/instruction cycle ............................. 10 figure 4-1: pic16c710 program memory map and stack .................................................. 11 figure 4-2: pic16c71/711 program memory map and stack .................................................. 11 figure 4-3: pic16c715 program memory map and stack .................................................. 11 figure 4-4: pic16c710/71 register file map ............. 12 figure 4-5: pic16c711 register file map .................. 13 figure 4-6: pic16c715 register file map .................. 13 figure 4-7: status register (address 03 h , 83 h ) .......... 17 figure 4-8: option register (address 81 h, 181h ) .... 18 figure 4-9: intcon register (address 0b h , 8b h ) ..... 19 figure 4-10: pie1 register (address 8c h ) ................... 20 figure 4-11: pir1 register (address 0c h ) ................... 21 figure 4-12: pcon register (address 8e h ), pic16c710/711 ........................................ 22 figure 4-13: pcon register (address 8e h ), pic16c715 ............................................... 22 figure 4-14: loading of pc in different situations ........ 23 figure 4-15: direct/indirect addressing ......................... 24 figure 5-1: block diagram of ra3:ra0 pins .............. 25 figure 5-2: block diagram of ra4/t0cki pin ............. 25 figure 5-3: block diagram of rb3:rb0 pins .............. 27 figure 5-4: block diagram of rb7:rb4 pins (pic16c71) ............................................... 28 figure 5-5: block diagram of rb7:rb4 pins (pic16c710/711/715) ............................... 28 figure 5-6: successive i/o operation ......................... 30 figure 6-1: timer0 block diagram .............................. 31 figure 6-2: timer0 timing: internal clock/ no prescale .............................................. 31 figure 6-3: timer0 timing: internal clock/ prescale 1:2 .............................................. 32 figure 6-4: timer0 interrupt timing ............................ 32 figure 6-5: timer0 timing with external clock ........... 33 figure 6-6: block diagram of the timer0/ wdt prescaler ......................................... 34 figure 7-1: adcon0 register (address 08 h ), pic16c710/71/711 ................................... 37 figure 7-2: adcon0 register (address 1f h ), pic16c715 ............................................... 38
1997 microchip technology inc. ds30390d -page 167 pic16c71x figure 7-3: adcon1 register, pic16c710/71/711 (address 88h), pic16c715 (address 9f h ) ........................ 38 figure 7-4: a/d block diagram .................................... 39 figure 7-5: analog input model ................................... 40 figure 7-6: a/d transfer function ............................... 45 figure 7-7: flowchart of a/d operation ....................... 45 figure 8-1: configuration word for pic16c 71 ............ 47 figure 8-2: configuration word, pic16c710/711 ........ 48 figure 8-3: configuration word, pic16c715 ............... 48 figure 8-4: crystal/ceramic resonator operation (hs, xt or lp osc configuration) ........... 49 figure 8-5: external clock input operation (hs, xt or lp osc configuration) ........... 49 figure 8-6: external parallel resonant crystal oscillator circuit ........................................ 51 figure 8-7: external series resonant crystal oscillator circuit ........................................ 51 figure 8-8: rc oscillator mode ................................... 51 figure 8-9: simplified block diagram of on-chip reset circuit .............................................. 52 figure 8-10: brown-out situations ................................. 53 figure 8-11: time-out sequence on power-up ( mclr not tied to v dd ): case 1 ............... 59 figure 8-12: time-out sequence on power-up ( mclr not tied to v dd ): case 2 ............. 59 figure 8-13: time-out sequence on power-up ( mclr tied to v dd ) .................................. 59 figure 8-14: external power-on reset circuit (for slow v dd power-up) ........................... 60 figure 8-15: external brown-out protection circuit 1 .... 60 figure 8-16: external brown-out protection circuit 2 .... 60 figure 8-17: interrupt logic, pic16c710, 71, 711 ......... 62 figure 8-18: interrupt logic, pic16c715 ....................... 62 figure 8-19: int pin interrupt timing ............................ 63 figure 8-20: watchdog timer block diagram ............... 65 figure 8-21: summary of watchdog timer registers ... 65 figure 8-22: wake-up from sleep through interrupt ..... 67 figure 8-23: typical in-circuit serial programming connection ................................................ 67 figure 9-1: general format for instructions ................ 69 figure 11-1: load conditions ........................................ 94 figure 11-2: external clock timing ............................... 95 figure 11-3: clkout and i/o timing ........................... 96 figure 11-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ....................................................... 97 figure 11-5: brown-out reset timing ............................ 97 figure 11-6: timer0 external clock timings ................. 98 figure 11-7: a /d conversion timing ........................... 100 figure 12-1: typical i pd vs. v dd (wdt disabled, rc mode) ..................... 101 figure 12-2: maximum i pd vs. v dd (wdt disabled, rc mode) ..................... 101 figure 12-3: typical i pd vs. v dd @ 25 c (wdt enabled, rc mode) ...................... 102 figure 12-4: maximum i pd vs. v dd (wdt enabled, rc mode) ...................... 102 figure 12-5: typical rc oscillator frequency vs. v dd .................................................... 102 figure 12-6: typical rc oscillator frequency vs. v dd .................................................... 102 figure 12-7: typical rc oscillator frequency vs. v dd .................................................... 102 figure 12-8: typical i pd vs. v dd brown-out detect enabled (rc mode) ................................ 103 figure 12-9: maximum i pd vs. v dd brown-out detect enabled (85 c to -40 c, rc mode) ........ 103 figure 12-10: typical i pd vs. timer1 enabled (32 k h z , rc0/rc1 = 33 p f/33 p f, rc mode) ............................................... 103 figure 12-11: maximum i pd vs. timer1 enabled (32 k h z , rc0/rc1 = 33 p f/33 p f, 85 c to -40 c, rc mode) ....................... 103 figure 12-12: typical i dd vs. frequency (rc mode @ 22 p f, 25 c) ..................... 104 figure 12-13: maximum i dd vs. frequency (rc mode @ 22 p f, -40 c to 85 c) ....... 104 figure 12-14: typical i dd vs. frequency (rc mode @ 100 p f, 25 c) ................... 105 figure 12-15: maximum i dd vs. frequency (rc mode @ 100 p f, -40 c to 85 c) ..... 105 figure 12-16: typical i dd vs. frequency (rc mode @ 300 p f, 25 c) ................... 106 figure 12-17: maximum i dd vs. frequency (rc mode @ 300 p f, -40 c to 85 c) ..... 106 figure 12-18: typical i dd vs . capacitance @ 500 k h z (rc mode) ........................... 107 figure 12-19: transconductance( gm ) of hs oscillator vs. v dd .............................. 107 figure 12-20: transconductance( gm ) of lp oscillator vs. v dd .............................. 107 figure 12-21: transconductance( gm ) of xt oscillator vs. v dd .............................. 107 figure 12-22: typical xtal startup time vs. v dd (lp mode, 25 c) ............................. 108 figure 12-23: typical xtal startup time vs. v dd (hs mode, 25 c) ............................. 108 figure 12-24: typical xtal startup time vs . v dd (xt mode, 25 c) ............................. 108 figure 12-25: typical i dd vs. frequency (lp mode, 25 c) ..................................... 109 figure 12-26: maximum i dd vs. frequency (lp mode, 85 c to -40 c) ....................... 109 figure 12-27: typical i dd vs . frequency (xt mode, 25 c) ..................................... 109 figure 12-28: maximum i dd vs . frequency (xt mode, -40 c to 85 c) ...................... 109 figure 12-29: typical i dd vs . frequency (hs mode, 25 c) .................................... 110 figure 12-30: maximum i dd vs . frequency (hs mode, -40 c to 85 c) ...................... 110 figure 13-1: load conditions ...................................... 117 figure 13-2: external clock timing ............................. 118 figure 13-3: c lko ut and i/o timing ......................... 119 figure 13-4: reset, watchdog timer, oscillator start-up timer, and power-up timer timing ..................................................... 120 figure 13-5: brown-out reset timing ......................... 120 figure 13-6: timer0 cl ock timings ............................. 121 figure 13-7: a/d conver sion timing ........................... 124 figure 14-1: typical i pd vs. v dd (wdt disabled, rc mode) ..................... 125 figure 14-2: maximum i pd vs. v dd (wdt disabled, rc mode) ..................... 125 figure 14-3: typical i pd vs. v dd @ 25 c (wdt enabled, rc mode) ...................... 126 figure 14-4: maximum i pd vs. v dd (wdt enabled, rc mode) ...................... 126 figure 14-5: typical rc oscillator frequency vs. v dd ......................................................... 126
pic16c71x ds30390d -page 168 1997 microchip technology inc. figure 14-6: typical rc oscillator frequency vs. v dd .......................................................... 126 figure 14-7: typical rc oscillator frequency vs. v dd .......................................................... 126 figure 14-8: typical i pd vs. v dd brown-out detect enabled (rc mode) ................................ 127 figure 14-9: maximum i pd vs. v dd brown-out detect enabled (85 c to -40 c, rc mode) ...................... 127 figure 14-10: typical i pd vs. timer1 enabled (32 k h z , rc0/rc1 = 33 p f/33 p f, rc mode) ....... 127 figure 14-11: maximum i pd vs. timer1 enabled (32 k h z , rc0/rc1 = 33 p f/33 p f, 85 c to -40 c, rc mode) ........................ 127 figure 14-12: typical i dd vs. frequency (rc mode @ 22 p f, 25 c) ...................... 128 figure 14-13: maximum i dd vs. frequency (rc mode @ 22 p f, -40 c to 85 c) ........ 128 figure 14-14: typical i dd vs. frequency (rc mode @ 100 p f, 25 c) .................... 129 figure 14-15: maximum i dd vs. frequency (rc mode @ 100 p f, -40 c to 85 c) ...... 129 figure 14-16: typical i dd vs. frequency (rc mode @ 300 p f, 25 c) .................... 130 figure 14-17: maximum i dd vs. frequency (rc mode @ 300 p f, -40 c to 85 c) ...... 130 figure 14-18: typical i dd vs . capacitance @ 500 k h z (rc mode) ............................................... 131 figure 14-19: transconductance( gm ) of hs oscillator vs. v dd .............................. 131 figure 14-20: transconductance( gm ) of lp oscillator vs. v dd ............................... 131 figure 14-21: transconductance( gm ) of xt oscillator vs. v dd .............................. 131 figure 14-22: typical xtal startup time vs. v dd (lp mode, 25 c) .............................. 132 figure 14-23: typical xtal startup time vs. v dd (hs mode, 25 c) ............................. 132 figure 14-24: typical xtal startup time vs . v dd (xt mode, 25 c) .............................. 132 figure 14-25: typical i dd vs. frequency (lp mode, 25 c) ..................................... 133 figure 14-26: maximum i dd vs. frequency (lp mode, 85 c to -40 c) ....................... 133 figure 14-27: typical i dd vs . frequency (xt mode, 25 c) ..................................... 133 figure 14-28: maximum i dd vs . frequency (xt mode, -40 c to 85 c) ....................... 133 figure 14-29: typical i dd vs . frequency (hs mode, 25 c) ..................................... 134 figure 14-30: maximum i dd vs . frequency (hs mode, -40 c to 85 c) ....................... 134 figure 15-1: load conditions ...................................... 140 figure 15-2: external clock timing ............................. 141 figure 15-3: clkout and i/o timing ......................... 142 figure 15-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ..................................................... 143 figure 15-5: timer0 external clock timings ............... 144 figure 15-6: a /d conversion timing ........................... 146 figure 16-1: typical rc oscillator frequency vs. temperature ............................................ 147 figure 16-2: typical rc oscillator frequency vs. v dd .......................................................... 147 figure 16-3: typical rc oscillator frequency vs. v dd .......................................................... 147 figure 16-4: typical rc oscillator frequency vs. v dd ......................................................... 148 figure 16-5: typical ipd vs. v dd watchdog timer disabled 25 c ......................................... 148 figure 16-6: typical ipd vs. v dd watchdog timer enabled 25 c .......................................... 148 figure 16-7: maximum ipd vs. v dd watchdog disabled .................................................. 149 figure 16-8: maximum ipd vs. v dd watchdog enabled ................................................... 149 figure 16-9: v th (input threshold voltage) of i/o pins vs. v dd ...................................... 149 figure 16-10: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd ............................. 150 figure 16-11: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd ................................. 150 figure 16-12: typical i dd vs. freq (ext clock, 25 c) .... 151 figure 16-13: maximum, i dd vs. freq (ext clock, -40 to +85 c) ......................................... 151 figure 16-14: maximum i dd vs. freq with a/d off (ext clock, -55 to +125 c) .................... 152 figure 16-15: wdt timer time-out period vs. v dd ...... 152 figure 16-16: transconductance ( gm ) of hs oscillator vs. v dd .............................. 152 figure 16-17: transconductance ( gm ) of lp oscillator vs. v dd .............................. 153 figure 16-18: transconductance ( gm ) of xt oscillator vs. v dd .............................. 153 figure 16-19: ioh vs. voh, v dd = 3v .......................... 153 figure 16-20: ioh vs. voh, v dd = 5v .......................... 153 figure 16-21: iol vs. vol, v dd = 3v ........................... 154 figure 16-22: iol vs. vol, v dd = 5v ........................... 154
1997 microchip technology inc. ds30390d -page 169 pic16c71x list of t ab les table 1-1: pic16c71x family of devices .................... 4 table 3-1: pic16c710/71/711/715 pinout description .................................................. 9 table 4-1: pic16c710/71/711 special function register summary .................................... 14 table 4-2: pic16c715 special function register summary ................................................... 15 table 5-1: porta functions ..................................... 26 table 5-2: summary of registers associated with porta ...................................................... 26 table 5-3: portb functions ..................................... 28 table 5-4: summary of registers associated with portb ...................................................... 29 table 6-1: registers associated with timer0 ............. 35 table 7-1: t ad vs . device operating frequencies, pic16c71 .................................................. 41 table 7-2: t ad vs . device operating frequencies, p ic16c710/711, pic16c715 .................... 41 table 7-3: registers/bits associated with a/d, pic16c710/71/711 .................................... 46 table 7-4: registers/bits associated with a/d, pic16c715 ................................................ 46 table 8-1: ceramic resonators, pic16c71 ............... 49 table 8-2: capacitor selection for crystal oscillator, pic16c71 ................................. 49 table 8-3: ceramic resonators, pic16c710/711/715 .................................. 50 table 8-4: capacitor selection for crystal oscillator, pic16c710/711/715 ................. 50 table 8-5: time-out in various situations, pic16c71 .................................................. 54 table 8-6: time-out in various situations, pic16c710/711/715 .................................. 54 table 8-7: status bits and their significance, pic16c71 .................................................. 55 table 8-8: status bits and their significance, pic16c710/711 ......................................... 55 table 8-9: status bits and their significance, pic16c715 ................................................ 55 table 8-10: reset condition for special registers, pic16c710/71/711 .................................... 56 table 8-11: reset condition for special registers, pic16c715 ................................................ 56 table 8-12: initialization conditions for all registers , pic16c710/71/711 .................................... 57 table 8-13: initialization conditions for all registers, pic16c715 ................................................ 58 table 9-1: opcode field descriptions ........................ 69 table 9-2: pic16cxx instruction set ......................... 70 table 10-1: development tools from microchip ......... 88 table 11-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ............................... 89 table 11-2: external clock timing requirements ........ 95 table 11-3: clkout and i/o timing requirements .... 96 table 11-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements ......... 97 table 11-5: timer0 external clock requirements ....... 98 table 11-6: a/d converter characteristics: pic16c710 /711 -04 (commercial, industrial, extended ) pic16c710 /711 -10 (commercial, industrial, extended ) pic16c710/711-20 (commercial, industrial, extended ) p ic16 l c710 /711 - 04 (commercial, industrial, extended) ........... 99 table 11-7: a/d conversion requirements ............... 100 table 12-1: rc oscillator frequencies ...................... 107 table 12-2: capacitor selection for crystal oscillators ............................................... 108 table 13-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ............................ 112 table 13-2: clock timing requirements .................... 118 table 13-3: clkout and i/o timing requirements . 119 table 13-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements ....... 120 table 13-5: timer0 clock requirements ................... 121 table 13-6: a/d converter characteristics: pic16c715-04 (commercial, industrial, extended) pic16c715-10 (commercial, industrial, extended) pic16c715-20 (commercial, industrial, extended) ........ 122 table 13-7: a/d converter characteristics: pic16lc715-04 (commercial, industrial) ................................................ 123 table 13-8: a/d conversion requirements ............... 124 table 14-1: rc oscillator frequencies ...................... 131 table 14-2: capacitor selection for crystal oscillators ............................................... 132 table 15-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ............................ 135 table 15-2: external clock timing requirements ..... 141 table 15-3: clkout and i/o timing requirements . 142 table 15-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements ......................................... 143 table 15-5: timer0 external clock requirements ..... 144 table 15-6: a/d converter characteristics ................ 145 table 15-7: a/d conversion requirements ............... 146 table 16-1: rc oscillator frequencies ...................... 148
pic16c71x ds30390d -page 170 1997 microchip technology inc. no tes:
1997 microchip technology inc. ds30272a -page 171 pic16c71x the procedure to connect will v ar y slightly from countr y to countr y . please chec k with y our local compuser v e agent f or details if y ou ha v e a prob lem. compuser v e ser vice allo w m ultiple users v ar ious baud r ates depending on the local point of access . the f ollo wing connect procedure applies in most loca- tions . 1. set y our modem to 8-bit, no par ity , and one stop (8n1). this is not the nor mal compuser v e setting which is 7e1. 2. dial y our local compuser v e access n umber . 3. depress the k e y and a garbage str ing will appear because compuser v e is e xpecting a 7e1 setting. 4. t ype +, depress the k e y and host name: will appear . 5. t ype mchipbbs , depress the k e y and y ou will be connected to the microchip bbs . in the united states , to nd the compuser v e phone n umber closest to y ou, set y our modem to 7e1 and dial (800) 848-4480 f or 300-2400 baud or (800) 331-7166 f or 9600-14400 baud connection. after the system responds with host name: ? type network , depress the k e y and f ollo w compuser v e's directions . f or v oice inf or mation (or calling from o v erseas), y ou ma y call (614) 723-1550 f or y our local compuser v e n umber . microchip regular ly uses the microchip bbs to distr ib u te technical inf or mation, application notes , source code , err ata sheets , b ug repor ts , and inter im patches f or microchip systems softw are products . f or each sig, a moder ator monitors , scans , and appro v es or disap- pro v es les submitted to the sig. no e x ecutab le les are accepted from the user comm unity in gener al to limit the spread of computer vir uses . systems inf ormation and upgrade hot line the systems inf or mation and upg r ade line pro vides system users a listing of the latest v ersions of all of microchip's de v elopment systems softw are products . plus , this line pro vides inf or mation on ho w customers can receiv e an y currently a v ailab le upg r ade kits .the hot line numbers are: 1-800-755-2345 f or u .s . and most of canada, and 1-602-786-7302 f or the rest of the w or ld. t rademarks: the microchip name , logo , pic , picst ar t , picmaster and pr o ma te are registered tr ademar ks of microchip t echnology incor por ated in the u .s .a. and other countr ies . fle x r om, mplab and fuzzy lab , are tr ademar ks and sqtp is a ser vice mar k of microchip in the u .s .a. fuzzy tech is a registered tr ademar k of inf or m softw are cor por ation. ibm, ibm pc-a t are registered tr ademar ks of inter national business machines cor p . p entium is a tr ademar k of intel cor por ation. windo ws is a tr ademar k and ms-dos , microsoft windo ws are registered tr ade- mar ks of microsoft cor por ation. compuser v e is a regis- tered tr ademar k of compuser v e incor por ated. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . on-line suppor t microchip pro vides tw o methods of on-line suppor t. these are the microchip bbs and the microchip w or ld wide w eb (www) site . use microchip's bulletin board ser vice (bbs) to get current inf or mation and help about microchip products . microchip pro vides the bbs comm unication channel f or y ou to use in e xtending y our technical staff with microcontroller and memor y e xper ts . t o pro vide y ou with the most responsiv e ser vice possib le , the microchip systems team monitors the bbs , posts the latest component data and softw are tool updates , pro vides technical help and embedded systems insights , and discusses ho w microchip products pro- vide project solutions . the w eb site , lik e the bbs , is used b y microchip as a means to mak e les and inf or mation easily a v ailab le to customers . t o vie w the site , the user m ust ha v e access to the inter net and a w eb bro wser , such as netscape or microsoft explorer . files are also a v ailab le f or ftp do wnload from our ftp site . connecting to the micr oc hip internet w eb site the microchip w eb site is a v ailab le b y using y our f a v or ite inter net bro wser to attach to: www .micr oc hip.com the le tr ansf er site is a v ailab le b y using an ftp ser- vice to connect to: ftp://ftp.futureone.com/pub/microchip the w eb site and le tr ansf er site pro vide a v ar iety of ser vices . users ma y do wnload les f or the latest de v elopment t ools , data sheets , application notes , user's guides , ar ticles and sample prog r ams . a v ar i- ety of microchip speci c b usiness inf or mation is also a v ailab le , including listings of microchip sales of ces , distr ib utors and f actor y representativ es . other data a v ailab le f or consider ation is: latest microchip press releases t echnical suppor t section with f requently ask ed questions design tips de vice err ata job p ostings microchip consultant prog r am member listing links to other useful w eb sites related to microchip products connecting to the micr oc hip bbs connect w or ldwide to the microchip bbs using either the inter net or the compuser v e comm unications net- w or k. internet: y ou can telnet or ftp to the microchip bbs at the address: mc hipbbs.micr oc hip.com compuser ve comm unications netw ork: when using the bbs via the compuser v e netw or k, in most cases , a local call is y our only e xpense . the microchip bbs connection does not use compuser v e membership ser vices , theref ore y ou do not need compuser v e membership to join microchip's bbs . the re is no charge f or connecting to the microchip bbs . 970301
pic16c71x ds30272a -page 172 1997 microchip technology inc. reader response it is our intention to pro vide y ou with the best documentation possib le to ensure successful use of y our microchip prod- uct. if y ou wish to pro vide y our comments on organization, clar ity , subject matter , and w a ys in which our documentation can better ser v e y ou, please f ax y our comments to the t echnical pub lications manager at (602) 786-7578. please list the f ollo wing inf or mation, and use this outline to pro vide us with y our comments about this data sheet . 1. what are the best f eatures of this document? 2. ho w does this document meet y our hardw are and softw are de v elopment needs? 3. do y ou nd the organization of this data sheet easy to f ollo w? if not, wh y? 4. what additions to the data sheet do y ou think w ould enhance the str ucture and subject? 5. what deletions from the data sheet could be made without aff ecting the o v er all usefulness? 6. is there an y incorrect or misleading inf or mation (what and where)? 7. ho w w ould y ou impro v e this document? 8. ho w w ould y ou impro v e our softw are , systems , and silicon products? t o: t echnical pub lications manager re: reader response t otal p ages sent f rom: name compan y address city / state / zip / countr y t elephone: (_______) _________ - _________ application (optional): w ould y ou lik e a reply? y n de vice: liter ature number : questions: f ax: (______) _________ - _________ ds30272a pic16c71x
1997 microchip technology inc. ds30272a -page 173 pic16c71x pic16c71x pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y ref er to the f actor y or the listed sales of ce . * jw de vices are uv er asab le and can be prog r ammed to an y de vice con gur ation. jw de vices meet the electr ical requirement of each oscillator type (including lc de vices). p ar t no . -xx x /xx xxx p attern: qtp , sqtp , code or special requirements p ac ka g e: jw = windo w ed cerdip so = soic sp = skinn y plastic dip p = pdip ss = ssop t emperature rang e: - = 0 c to +70 c i = -40 c to +85 c e = -40 c to +125 c frequenc y rang e: 04 = 200 khz (pic16c7x-04) 04 = 4 mhz 10 = 10 mhz 20 = 20 mhz de vice pic16c7x : v dd r ange 4.0v to 6.0v pic16c7xt : v dd r ange 4.0v to 6.0v (t ape/reel) pic16lc7x : v dd r ange 2.5v to 6.0v pic16lc7xt : v dd r ange 2.5v to 6.0v (t ape/reel) examples a) pic16c71 - 04/p 301 commercial t emp ., pdip p ac kage , 4 mhz, nor mal v dd limits , qtp patter n #301 b) sales and suppor t products suppor ted b y a preliminar y data sheet ma y possib ly ha v e an err ata sheet descr ibing minor oper ational diff erences and recommended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: y our local microchip sales of ce (see belo w) the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277 the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required). please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using. f or latest v ersion inf or mation and upg r ade kits f or microchip de v elopment t ools , please call 1-800-755-2345 or 1-602-786-7302. 1. 2. 3.
pic16c71x ds30272a -page 174 1997 microchip technology inc. no tes:
1997 microchip technology inc. ds30272a -page 175 pic16c71x no tes:
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

▲Up To Search▲

Price & Availability of PIC16C71-04JW

	To Download PIC16C71-04JW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .